X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/45fa96c0a2fd6e490690cff69dd694a3dce3ab35..056fa141e0cb4366a264458bb8b927126ef85aeb:/ICache.v diff --git a/ICache.v b/ICache.v index 3a9f144..8b9eac3 100644 --- a/ICache.v +++ b/ICache.v @@ -10,7 +10,7 @@ module ICache( output reg [31:0] rd_data, /* bus interface */ - output reg bus_req, + output wire bus_req, input bus_ack, output reg [31:0] bus_addr, input [31:0] bus_rdata, @@ -30,24 +30,24 @@ module ICache( reg cache_valid [15:0]; reg [21:0] cache_tags [15:0]; - reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */]; + reg [31:0] cache_data [255:0 /* {line, word} */]; //synthesis attribute ram_style of cache_data is distributed - reg [4:0] i; + integer i; initial for (i = 0; i < 16; i = i + 1) + begin cache_valid[i[3:0]] = 0; + cache_tags[i[3:0]] = 0; + end wire [5:0] rd_didx = rd_addr[5:0]; wire [3:0] rd_didx_word = rd_didx[5:2]; wire [3:0] rd_idx = rd_addr[9:6]; wire [21:0] rd_tag = rd_addr[31:10]; - wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag); + reg [31:0] prev_rd_addr = 32'hFFFFFFFF; - always @(*) begin /* XXX does this work nowadays? */ - rd_wait = rd_req && !cache_hit; - rd_data = cache_data[rd_idx][rd_didx_word]; - end + wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag); reg [3:0] cache_fill_pos = 0; assign bus_req = rd_req && !cache_hit; /* xxx, needed for Verilator */ @@ -59,16 +59,27 @@ module ICache( bus_addr = 0; bus_rd = 0; end + + wire [31:0] curdata = cache_data[{rd_idx,rd_didx_word}]; + always @(*) begin + rd_wait = rd_req && !cache_hit; + rd_data = curdata; + end - always @(posedge clk) - if (rd_req && !cache_hit) begin - if (bus_ready) begin /* Started the fill, and we have data. */ - cache_data[rd_idx][cache_fill_pos] <= bus_rdata; - cache_fill_pos <= cache_fill_pos + 1; - if (cache_fill_pos == 15) begin /* Done? */ - cache_tags[rd_idx] <= rd_tag; - cache_valid[rd_idx] <= 1; - end - end + always @(posedge clk) begin + prev_rd_addr <= {rd_addr[31:6], 6'b0}; + if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */ + cache_fill_pos <= 0; + else if (rd_req && !cache_hit && bus_ack && bus_ready) begin + $display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata); + cache_data[{rd_idx,cache_fill_pos}] <= bus_rdata; + cache_fill_pos <= cache_fill_pos + 1; + if (cache_fill_pos == 15) begin /* Done? */ + cache_tags[rd_idx] <= rd_tag; + cache_valid[rd_idx] <= 1; + $display("ICACHE: Fill complete for line %x, tag %x", rd_idx, rd_tag); + end else + cache_valid[rd_idx] <= 0; end + end endmodule