X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/42c1e61007ac83838a25dfeb0f672213f75ed0bb..b7359a807e88320755edab8987c269a0b9c83f26:/Decode.v diff --git a/Decode.v b/Decode.v index 42ae993..22c6eae 100644 --- a/Decode.v +++ b/Decode.v @@ -26,18 +26,23 @@ module Decode( wire [31:0] shift_oper; wire [31:0] shift_res; wire shift_cflag_out; + wire [31:0] rotate_res; assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0; assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1; assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */ - IHATEARMSHIFT blowme(.insn(insn), - .operand(regs1), - .reg_amt(regs2), - .cflag_in(incpsr[`CPSR_C]), - .res(shift_res), - .cflag_out(shift_cflag_out)); - + IREALLYHATEARMSHIFT blowme(.insn(insn), + .operand(regs1), + .reg_amt(regs2), + .cflag_in(incpsr[`CPSR_C]), + .res(shift_res), + .cflag_out(shift_cflag_out)); + + SuckLessRotator whirr(.oper({24'b0, insn[7:0]}), + .amt(insn[11:8]), + .res(rotate_res)); + always @(*) casez (insn) 32'b????000000??????????????1001????, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ @@ -152,7 +157,7 @@ module Decode( end 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */ if(insn[25]) begin /* the constant case */ - op0_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0})); + op0_out = rotate_res; end else begin op0_out = regs0; end @@ -161,7 +166,7 @@ module Decode( op0_out = regs0; if(insn[25]) begin /* the constant case */ carry_out = incpsr[`CPSR_C]; - op1_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0})); + op1_out = rotate_res; end else begin carry_out = shift_cflag_out; op1_out = shift_res; @@ -226,7 +231,7 @@ module Decode( endmodule -module IHATEARMSHIFT( +module IREALLYHATEARMSHIFT( input [31:0] insn, input [31:0] operand, input [31:0] reg_amt, @@ -235,41 +240,99 @@ module IHATEARMSHIFT( output cflag_out ); wire [5:0] shift_amt; - wire elanus; + wire rshift_cout, is_arith, is_rot; + wire [31:0] rshift_res; + + assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */ + : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */ + SuckLessShifter biteme(.oper(operand), + .carryin(cflag_in), + .amt(shift_amt), + .is_arith(is_arith), + .is_rot(is_rot), + .res(rshift_res), + .carryout(rshift_cout)); - /* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */ always @(*) - if(insn[4]) begin - shift_amt = {|reg_amt[7:5], reg_amt[4:0]}; - elanus = 1'b1; - end else begin - shift_amt = {insn[11:7] == 5'b0, insn[11:7]}; - elanus = 1'b0; + case (insn[6:5]) + `SHIFT_LSL: begin + /* meaningless */ + is_rot = 1'b0; + is_arith = 1'b0; end - + `SHIFT_LSR: begin + is_rot = 1'b0; + is_arith = 1'b0; + end + `SHIFT_ASR: begin + is_rot = 1'b0; + is_arith = 1'b1; + end + `SHIFT_ROR: begin + is_rot = 1'b1; + is_arith = 1'b0; + end + endcase + always @(*) case (insn[6:5]) /* shift type */ - `SHIFT_LSL: begin - {cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]}; - end + `SHIFT_LSL: + {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]}; `SHIFT_LSR: begin - {res, cflag_out} = {operand, cflag_in} >> shift_amt; + res = rshift_res; + cflag_out = rshift_cout; end `SHIFT_ASR: begin - {res, cflag_out} = {operand, cflag_in} >> shift_amt | (operand[31] ? ~(33'h1FFFFFFFF >> shift_amt) : 33'b0); + res = rshift_res; + cflag_out = rshift_cout; end `SHIFT_ROR: begin - if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */ + if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */ res = {cflag_in, operand[31:1]}; cflag_out = operand[0]; - end else if(shift_amt == 6'b0) begin - res = operand; - cflag_out = cflag_in; end else begin - res = operand >> shift_amt[4:0] | operand << (5'b0 - shift_amt[4:0]); - cflag_out = operand[shift_amt[4:0] - 5'b1]; + res = rshift_res; + cflag_out = rshift_cout; end end endcase endmodule + +module SuckLessShifter( + input [31:0] oper, + input carryin, + input [5:0] amt, + input is_arith, + input is_rot, + output [31:0] res, + output carryout +); + + wire [32:0] stage1, stage2, stage3, stage4, stage5; + + wire pushbits = is_arith & oper[31]; + + /* do a barrel shift */ + assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin}; + assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1; + assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2; + assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3; + assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4; + assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5; + +endmodule + +module SuckLessRotator( + input [31:0] oper, + input [3:0] amt, + output [31:0] res +); + + wire [31:0] stage1, stage2, stage3; + assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper; + assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1; + assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2; + assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3; + +endmodule