X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/3550fbf2e864e370a59d7b6b546f93f4016ebd6b..fd003c7a793fb17fb6dc7ba52873b883b28a578b:/system.v

diff --git a/system.v b/system.v
index 2467ad7..f134ffc 100644
--- a/system.v
+++ b/system.v
@@ -1,7 +1,15 @@
-`define BUS_ICACHE 0
-`define BUS_DCACHE 1
+`define BUS_ICACHE 1
+`define BUS_DCACHE 0
 
-module System(input clk);
+module System(input clk
+`ifdef verilator
+`else
+	, output wire [8:0] sys_odata,
+	input [8:0] sys_idata,
+	output wire sys_tookdata
+`endif
+	);
+	
 	wire [7:0] bus_req;
 	wire [7:0] bus_ack;
 	wire [31:0] bus_addr;
@@ -12,7 +20,7 @@ module System(input clk);
 
 	wire bus_req_icache;
 	wire bus_req_dcache;
-	assign bus_req = {6'b0, bus_req_dcache, bus_req_icache};
+	assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
 	wire bus_ack_icache = bus_ack[`BUS_ICACHE];
 	wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
 	
@@ -60,6 +68,7 @@ module System(input clk);
 	wire [31:0] execute_out_write_data;
 	wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
 	wire [31:0] execute_out_cpsr, execute_out_spsr;
+	wire execute_out_cpsrup;
 	
 	wire jmp_out_execute, jmp_out_writeback;
 	wire [31:0] jmppc_out_execute, jmppc_out_writeback;
@@ -70,6 +79,7 @@ module System(input clk);
 	wire [3:0] memory_out_write_num;
 	wire [31:0] memory_out_write_data;
 	wire [31:0] memory_out_cpsr, memory_out_spsr;
+	wire memory_out_cpsrup;
 	
 	wire [31:0] writeback_out_cpsr, writeback_out_spsr;
 
@@ -125,7 +135,12 @@ module System(input clk);
 		.bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
 		.bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
 
-	BlockRAM blockram(
+`ifdef verilator
+	BigBlockRAM
+`else
+	BlockRAM
+`endif
+	blockram(
 		.clk(clk),
 		.bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
 		.bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
@@ -177,7 +192,7 @@ module System(input clk);
 		.jmp(jmp_out_execute), .jmppc(jmppc_out_execute),
 		.outpc(pc_out_execute), .outinsn(insn_out_execute),
 		.outop0(execute_out_op0), .outop1(execute_out_op1), .outop2(execute_out_op2),
-		.outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr));
+		.outcpsr(execute_out_cpsr), .outspsr(execute_out_spsr), .outcpsrup(execute_out_cpsrup));
 	assign execute_out_backflush = jmp;
 	
 	assign cp_insn = insn_out_execute;
@@ -189,25 +204,30 @@ module System(input clk);
 		.st_read(regfile_read_3), .st_data(regfile_rdata_3),
 		.inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
 		.op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
-		.spsr(execute_out_spsr), .cpsr(execute_out_cpsr),
+		.spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
 		.write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
 		.outstall(stall_cause_memory), .outbubble(bubble_out_memory), 
 		.outpc(pc_out_memory), .outinsn(insn_out_memory),
 		.out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num), 
 		.out_write_data(memory_out_write_data),
 		.cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
-		.outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr) /* XXX data_size */);
+		.outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);
 	
 	Terminal terminal(	
 		.clk(clk),
 		.cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
-		.cp_read(cp_read_terminal), .cp_write(cp_write));
+		.cp_read(cp_read_terminal), .cp_write(cp_write)
+`ifdef verilator
+`else
+		, .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
+`endif
+		);
 	
 	Writeback writeback(
 		.clk(clk),
 		.inbubble(bubble_out_memory),
 		.write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
-		.cpsr(memory_out_cpsr), .spsr(memory_out_spsr),
+		.cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
 		.regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
 		.outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr), 
 		.jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
@@ -220,7 +240,7 @@ module System(input clk);
 		$display("------------------------------------------------------------------------------");
 		$display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
 		$display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
-		$display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
+		$display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
 		$display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
 		$display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
 		$display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);