X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/149bcd1aae858c157cb51b351187c66a99410d6d..4dc317445bd5132ca57744d7faf27731ea10d3b9:/Execute.v

diff --git a/Execute.v b/Execute.v
index cefc4ef..6582581 100644
--- a/Execute.v
+++ b/Execute.v
@@ -23,7 +23,10 @@ module Execute(
 	output reg [3:0] write_num = 4'bxxxx,
 	output reg [31:0] write_data = 32'hxxxxxxxx,
 	output reg [31:0] jmppc,
-	output reg jmp
+	output reg jmp,
+	output reg [31:0] outpc,
+	output reg [31:0] outinsn,
+	output reg [31:0] outop0, outop1, outop2
 	);
 	
 	reg mult_start;
@@ -54,7 +57,7 @@ module Execute(
 		.in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
 		.setflags(alu_setflags), .shifter_carry(carry),
 		.result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
-	
+
 	always @(posedge clk)
 	begin
 		if (!stall)
@@ -65,8 +68,20 @@ module Execute(
 			write_reg <= next_write_reg;
 			write_num <= next_write_num;
 			write_data <= next_write_data;
+			outpc <= pc;
+			outinsn <= insn;
+			outop0 <= op0;
+			outop1 <= op1;
+			outop2 <= op2;
 		end
 	end
+	
+	reg delayedflush = 0;
+	always @(posedge clk)
+		if (flush && outstall /* halp! I can't do it now, maybe later? */)
+			delayedflush <= 1;
+		else if (!outstall /* anything has been handled this time around */)
+			delayedflush <= 0;
 
 	reg prevstall = 0;
 	always @(posedge clk)
@@ -75,7 +90,7 @@ module Execute(
 	always @(*)
 	begin
 		outstall = stall;
-		next_outbubble = inbubble | flush;
+		next_outbubble = inbubble | flush | delayedflush;
 		next_outcpsr = cpsr;
 		next_outspsr = spsr;
 		next_write_reg = 0;
@@ -93,7 +108,7 @@ module Execute(
 		alu_setflags = 1'bx;
 
 		jmp = 1'b0;
-		jmppc = 32'hxxxxxxxx;
+		jmppc = 32'h00000000;
 
 		casez (insn)
 		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
@@ -106,8 +121,8 @@ module Execute(
 				mult_in1 = op2 /* Rs */;
 				$display("New MUL instruction");
 			end
-			outstall = stall | ((!prevstall | !mult_done) && !inbubble);
-			next_outbubble = inbubble | !mult_done | !prevstall;
+			outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
+			next_outbubble = next_outbubble | !mult_done | !prevstall;
 			next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
 			next_write_reg = 1;
 			next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
@@ -163,13 +178,15 @@ module Execute(
 		begin end
 		`DECODE_BRANCH:
 		begin
-			jmppc = pc + op0 + 32'h8;
-			if(insn[24]) begin
-				next_write_reg = 1;
-				next_write_num = 4'hE; /* link register */
-				next_write_data = pc + 32'h4;
+			if(!inbubble && !flush && !delayedflush) begin
+				jmppc = pc + op0 + 32'h8;
+				if(insn[24]) begin
+					next_write_reg = 1;
+					next_write_num = 4'hE; /* link register */
+					next_write_data = pc + 32'h4;
+				end
+				jmp = 1'b1;
 			end
-			jmp = 1'b1;
 		end                     /* Branch */
 		`DECODE_LDCSTC,		/* Coprocessor data transfer */
 		`DECODE_CDP,		/* Coprocessor data op */
@@ -234,14 +251,14 @@ module ALU(
 	output reg [31:0] cpsr_out,
 	output reg setres
 );
-	wire [31:0] res;
-	wire flag_n, flag_z, flag_c, flag_v, setres;
+	reg [31:0] res;
+	reg flag_n, flag_z, flag_c, flag_v;
 	wire [32:0] sum, diff, rdiff;
 	wire sum_v, diff_v, rdiff_v;
 
 	assign sum = {1'b0, in0} + {1'b0, in1};
 	assign diff = {1'b0, in0} - {1'b0, in1};
-	assign rdiff = {1'b0, in1} + {1'b0, in0};
+	assign rdiff = {1'b0, in1} - {1'b0, in0};
 	assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
 	assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
 	assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);