X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/0ede28efad9b536d699c10d257eb2b6a3804919f..0e3732b3e54e92cd569cd79f41819a7336f1c6ea:/Issue.v

diff --git a/Issue.v b/Issue.v
index 8fba308..7b281a3 100644
--- a/Issue.v
+++ b/Issue.v
@@ -167,7 +167,7 @@ module Issue(
 						(idxbit(rs) | idxbit(rm)) :
 						(idxbit(rm)))) |
 				(((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
-			def_cpsr = insn[20] /* S */ | alu_is_logical(alu_opc);
+			def_cpsr = insn[20] /* S */;
 			def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
 		end
 		`DECODE_LDRSTR_UNDEFINED:	/* Undefined. I hate ARM */
@@ -282,24 +282,33 @@ module Issue(
 		waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
 		waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
 		
-		outstall = waiting && !inbubble;	/* Happens in an always @*, because it is an exception. */
+		outstall = ((waiting && !inbubble) || stall) && !flush;	/* Happens in an always @*, because it is an exception. */
 	end
 	
 	/* Actually do the issue. */
 	always @(posedge clk)
 	begin
-		cpsr_inflight[0] <= cpsr_inflight[1];	/* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
-		cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;
-		regs_inflight[0] <= regs_inflight[1];
-		regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
-		
 		if (waiting)
-		begin
 			$display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
-		end
 
-		outbubble <= inbubble | waiting | !condition_met;
-		outpc <= inpc;
-		outinsn <= insn;
+		if(flush)
+		begin
+			cpsr_inflight[0] = 1'b0;
+			cpsr_inflight[1] = 1'b0;
+			regs_inflight[0] = 16'b0;
+			regs_inflight[1] = 16'b0;
+			outbubble <= 1'b1;
+		end
+		else if (!stall)
+		begin
+			cpsr_inflight[0] <= cpsr_inflight[1];	/* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
+			cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;
+			regs_inflight[0] <= regs_inflight[1];
+			regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
+			
+			outbubble <= inbubble | waiting | !condition_met;
+			outpc <= inpc;
+			outinsn <= insn;
+		end
 	end
 endmodule