X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/0bc7ede9b1671ea0e70adb678d1d453cbb636fbd..326fd4c33d4331252af93af8ee3fe5dbb7ff0d3f:/Decode.v

diff --git a/Decode.v b/Decode.v
index 506480d..fd8554b 100644
--- a/Decode.v
+++ b/Decode.v
@@ -63,58 +63,82 @@ module Decode(
 			rpc = 32'hxxxxxxxx;
 		endcase
 
-	always @(*)
+	always @(*) begin
+		read_0 = 4'hx;
+		read_1 = 4'hx;
+		read_2 = 4'hx;
+		
 		casez (insn)
 		32'b????000000??????????????1001????:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+		begin
 			read_0 = insn[15:12]; /* Rn */
+			read_1 = insn[3:0];   /* Rm */
+			read_2 = insn[11:8];  /* Rs */
+		end
 //		32'b????00001???????????????1001????,	/* Multiply long */
 //			read_0 = insn[11:8]; /* Rn */
+//			read_1 = insn[3:0];   /* Rm */
+//			read_2 = 4'b0;       /* anyus */
 		32'b????00010?001111????000000000000,	/* MRS (Transfer PSR to register) */
 		32'b????00010?101001111100000000????,	/* MSR (Transfer register to PSR) */
 		32'b????00?10?1010001111????????????:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
-			read_0 = 4'hx;
+		begin end	/* Everything stays x'ed out. */
 		32'b????00??????????????????????????:	/* ALU */
+		begin
 			read_0 = insn[19:16]; /* Rn */
+			read_1 = insn[3:0];   /* Rm */
+			read_2 = insn[11:8];  /* Rs for shift */
+		end
 		32'b????00010?00????????00001001????:	/* Atomic swap */
+		begin
 			read_0 = insn[19:16]; /* Rn */
+			read_1 = insn[3:0];   /* Rm */
+		end
 		32'b????000100101111111111110001????:	/* Branch and exchange */
 			read_0 = insn[3:0];   /* Rn */
 		32'b????000??0??????????00001??1????:	/* Halfword transfer - register offset */
+		begin
 			read_0 = insn[19:16];
-		32'b????000??1??????????00001??1????:	/* Halfword transfer - register offset */
+			read_1 = insn[3:0];
+		end
+		32'b????000??1??????????00001??1????:	/* Halfword transfer - immediate offset */
+		begin
 			read_0 = insn[19:16];
+			read_1 = insn[3:0];
+		end
 		32'b????011????????????????????1????:	/* Undefined. I hate ARM */
-			read_0 = 4'hx;
+		begin end
 		32'b????01??????????????????????????:	/* Single data transfer */
+		begin
 			read_0 = insn[19:16]; /* Rn */
+			read_1 = insn[3:0];   /* Rm */
+		end
 		32'b????100?????????????????????????:	/* Block data transfer */
 			read_0 = insn[19:16];
 		32'b????101?????????????????????????:	/* Branch */
-			read_0 = 4'hx;
+		begin end
 		32'b????110?????????????????????????:	/* Coprocessor data transfer */
 			read_0 = insn[19:16];
 		32'b????1110???????????????????0????,	/* Coprocessor data op */
 		32'b????1110???????????????????1????,	/* Coprocessor register transfer */
 		32'b????1111????????????????????????:	/* SWI */
-			read_0 = 4'hx;
+		begin end
 		default:
-			read_0 = 4'hx;
+			$display("Undecoded instruction");
 		endcase
-
-	always @ (*) begin
+	end
+	
+	always @(*) begin
+		op1_res = 32'hxxxxxxxx;
+		cpsr = 32'hxxxxxxxx;
 		casez (insn)
 		32'b????000000??????????????1001????: begin /* Multiply */
-			read_1 = insn[3:0];   /* Rm */
-			read_2 = insn[11:8];  /* Rs */
 			op1_res = regs1;
 			cpsr = incpsr;
 		end
-/*		32'b????00001???????????????1001????: begin * Multiply long *
-			
-			read_1 = insn[3:0];  * Rm *
-			read_2 = 4'b0;       * anyus *
-			op1_res = regs1;
-		end*/
+//		32'b????00001???????????????1001????: begin /* Multiply long */
+//			op1_res = regs1;
+//		end
 		32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
 			cpsr = incpsr;
 		end
@@ -125,8 +149,6 @@ module Decode(
 			cpsr = incpsr;
                 end
 		32'b????00??????????????????????????: begin /* ALU */
-			read_1 = insn[3:0];   /* Rm */
-			read_2 = insn[11:8];  /* Rs for shift */
 			if(insn[25]) begin     /* the constant case */
 				cpsr = incpsr;
 				op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
@@ -136,22 +158,16 @@ module Decode(
 			end
 		end
 		32'b????00010?00????????00001001????: begin /* Atomic swap */
-			read_1 = insn[3:0];   /* Rm */
-			read_2 = 4'b0;        /* anyus */
 			op1_res = regs1;
 		end
 		32'b????000100101111111111110001????: begin /* Branch and exchange */
 			cpsr = incpsr;
 		end
 		32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
-			read_1 = insn[3:0];
-			read_2 = 4'b0;
 			op1_res = regs1;
 			cpsr = incpsr;
 		end
 		32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
-			
-			read_1 = insn[3:0];
 			op1_res = {24'b0, insn[11:8], insn[3:0]};
 			cpsr = incpsr;
 		end
@@ -159,7 +175,6 @@ module Decode(
 			/* eat shit */
 		end
 		32'b????01??????????????????????????: begin /* Single data transfer */
-			read_1 = insn[3:0];   /* Rm */
 			if(insn[25]) begin
 				op1_res = {20'b0, insn[11:0]};
 				cpsr = incpsr;