X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/09e28f01bc93c7e5f280dbef0be909dfffad07c8..48775efdc0074dd9a772e37ae43adf58b5c9be8c:/Issue.v

diff --git a/Issue.v b/Issue.v
index 628ef08..fcc2c0c 100644
--- a/Issue.v
+++ b/Issue.v
@@ -5,17 +5,17 @@ module Issue(
 	input Nrst,	/* XXX not used yet */
 	
 	input stall,	/* pipeline control */
-	input flush,
+	input flush,	/* XXX not used yet */
 	
 	input inbubble,	/* stage inputs */
 	input [31:0] insn,
 	input [31:0] inpc,
 	input [31:0] cpsr,
 	
-	output reg outstall,	/* stage outputs */
-	output reg outbubble,
-	output reg [31:0] outpc,
-	output reg [31:0] outinsn
+	output reg outstall = 0,	/* stage outputs */
+	output reg outbubble = 1,
+	output reg [31:0] outpc = 0,
+	output reg [31:0] outinsn = 0
 	/* XXX other? */
 	);
 	
@@ -264,23 +264,37 @@ module Issue(
 	reg waiting_regs;
 	wire waiting = waiting_cpsr | waiting_regs;
 	
+	initial
+	begin
+		cpsr_inflight[0] = 0;
+		cpsr_inflight[1] = 0;
+		regs_inflight[0] = 0;
+		regs_inflight[1] = 0;
+	end
+		
 	always @(*)
 	begin
 		waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
 		waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
+		
+		outstall = waiting && !inbubble;	/* Happens in an always @*, because it is an exception. */
 	end
 	
 	/* Actually do the issue. */
 	always @(posedge clk)
 	begin
 		cpsr_inflight[0] <= cpsr_inflight[1];	/* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
-		cpsr_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_cpsr;
+		cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;
 		regs_inflight[0] <= regs_inflight[1];
-		regs_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_regs;
+		regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
+		
+		if (waiting)
+		begin
+			$display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
+		end
 
 		outbubble <= inbubble | waiting | !condition_met;
 		outpc <= inpc;
 		outinsn <= insn;
-		outstall <= waiting;
 	end
 endmodule