X-Git-Url: http://git.joshuawise.com/firearm.git/blobdiff_plain/03cf736e2c85ee881927ceef1fae0542c85077da..ac3ba6ad6814e7d0cfb296d8b699f5b3ed2632a5:/Decode.v

diff --git a/Decode.v b/Decode.v
index 359bbc0..2c22746 100644
--- a/Decode.v
+++ b/Decode.v
@@ -2,6 +2,7 @@
 
 module Decode(
 	input clk,
+	input stall,
 	input [31:0] insn,
 	input [31:0] inpc,
 	input [31:0] incpsr,
@@ -10,6 +11,7 @@ module Decode(
 	output reg [31:0] op1,
 	output reg [31:0] op2,
 	output reg carry,
+	output reg [31:0] outcpsr,
 	output reg [31:0] outspsr,
 
 	output reg [3:0] read_0,
@@ -63,11 +65,12 @@ module Decode(
 		`DECODE_BRANCH,			/* Branch */
 		`DECODE_LDCSTC,			/* Coprocessor data transfer */
 		`DECODE_CDP,			/* Coprocessor data op */
-		`DECODE_MRCMCR,			/* Coprocessor register transfer */
 		`DECODE_SWI:			/* SWI */
-			rpc = inpc - 8;
+			rpc = inpc + 8;
+		`DECODE_MRCMCR:			/* Coprocessor register transfer */
+			rpc = inpc + 12;
 		`DECODE_ALU:			/* ALU */
-			rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
+			rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
 		default:			/* X everything else out */
 			rpc = 32'hxxxxxxxx;
 		endcase
@@ -137,16 +140,20 @@ module Decode(
 		begin
 			read_0 = insn[19:16];
 			read_1 = insn[3:0];
-			
+			read_2 = insn[15:12];
+
 			op0_out = regs0;
 			op1_out = regs1;
+			op2_out = regs2;
 		end
 		`DECODE_ALU_HDATA_IMM:	/* Halfword transfer - immediate offset */
 		begin
 			read_0 = insn[19:16];
+			read_1 = insn[15:12];
 			
 			op0_out = regs0;
 			op1_out = {24'b0, insn[11:8], insn[3:0]};
+			op2_out = regs1;
 		end
 		`DECODE_ALU:		/* ALU */
 		begin
@@ -171,15 +178,17 @@ module Decode(
 		begin
 			read_0 = insn[19:16]; /* Rn */
 			read_1 = insn[3:0];   /* Rm */
+			read_2 = insn[15:12];
 			
 			op0_out = regs0;
-			if(insn[25]) begin
+			if(!insn[25] /* immediate */) begin
 				op1_out = {20'b0, insn[11:0]};
 				carry_out = incpsr[`CPSR_C];
 			end else begin
 				op1_out = shift_res;
 				carry_out = shift_cflag_out;
 			end
+			op2_out = regs2;
 		end
 		`DECODE_LDMSTM:		/* Block data transfer */
 		begin
@@ -218,11 +227,15 @@ module Decode(
 
 	
 	always @ (posedge clk) begin
-		op0 <= op0_out;   /* Rn - always */
-		op1 <= op1_out; /* 'operand 2' - Rm */
-		op2 <= op2_out;   /* thirdedge - Rs */
-		carry <= carry_out;
-		outspsr <= inspsr;
+		if (!stall)
+		begin
+			op0 <= op0_out;   /* Rn - always */
+			op1 <= op1_out; /* 'operand 2' - Rm */
+			op2 <= op2_out;   /* thirdedge - Rs */
+			carry <= carry_out;
+			outcpsr <= incpsr;
+			outspsr <= inspsr;
+		end
 	end
 
 endmodule