Issue, system, RegFile: First pass at adding resets.

[firearm.git] / BlockRAM.v

diff --git a/BlockRAM.v b/BlockRAM.v
index a86ec7592ad0f5a315977d54319e2b3ad56cd6df..091c749aef6f8f482bfbfe3025c881608d1696ff 100644 (file)
--- a/BlockRAM.v
+++ b/BlockRAM.v
@@ -35,7 +35,7 @@ module BlockRAM(
                
                /* This is not allowed to be conditional -- stupid Xilinx
                 * blockram. */
-               temprdata <= data[ramaddr[13:2]];
+               temprdata <= (bus_wr && decode) ? bus_wdata : data[ramaddr[13:2]];
                lastread <= ramaddr;
        end
 endmodule