lsrh_state <= next_lsrh_state;
if (do_rd_data_latch)
rd_data_latch <= rd_data;
+ swp_oldval <= next_swp_oldval;
prevaddr <= addr;
end
end
`LSM_MEMIO: begin
outstall = 1'b1;
- if(next_regs == 16'b0) begin
+ if(next_regs == 16'b0 && !rw_wait) begin
next_lsm_state = `LSM_BASEWB;
end
`LSM_SETUP:
next_write_reg = 1'b0;
`LSM_MEMIO: begin
- if(insn[20]) begin
+ if(insn[20] /* L */) begin
next_write_reg = !rw_wait;
next_write_num = cur_reg;
next_write_data = rd_data;
always @(*)
begin
st_read = 4'hx;
- offset = prev_offset;
cur_reg = prev_reg;
next_regs = regs;
lsrh_rddata_s1 = 16'hxxxx;
lsrh_rddata_s2 = 8'hxx;
next_swp_oldval = swp_oldval;
+
+ align_s1 = 32'hxxxxxxxx;
+ align_s2 = 32'hxxxxxxxx;
+ align_rddata = 32'hxxxxxxxx;
/* XXX shit not given about endianness */
casez(insn)