Memory: Clean up some sadness with wr_data where no data would ever get wr'ed on...

[firearm.git] / Memory.v

diff --git a/Memory.v b/Memory.v
index 985541148a766ac8e12c7920e8a9cc3025763bab..3c7ec970ab707a8b682af29ab09e52ab3172b8a4 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -258,7 +258,7 @@ module Memory(
                                        next_lsm_state = `LSM_BASEWB;
                                end
                                
                                        next_lsm_state = `LSM_BASEWB;
                                end
                                

-                               $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
+                               $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, st_data, busaddr);

                        end
                        `LSM_BASEWB: begin
                                outstall = 1;
                        end
                        `LSM_BASEWB: begin
                                outstall = 1;


@@ -480,7 +480,6 @@ module Memory(
                        2'b11: /* signed half */
                                data_size = 3'b010;
                        default: begin
                        2'b11: /* signed half */
                                data_size = 3'b010;
                        default: begin

-                               wr_data = 32'hxxxxxxxx;

                                data_size = 3'bxxx;
                        end
                        endcase
                                data_size = 3'bxxx;
                        end
                        endcase


@@ -500,7 +499,6 @@ module Memory(
                        addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
                        raddr = insn[24] ? addr : op0; /* pre/post increment */
                        busaddr = raddr;
                        addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
                        raddr = insn[24] ? addr : op0; /* pre/post increment */
                        busaddr = raddr;

-                       wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;

                        data_size = insn[22] ? 3'b001 : 3'b100;
                        case (lsr_state)
                        `LSR_MEMIO: begin
                        data_size = insn[22] ? 3'b001 : 3'b100;
                        case (lsr_state)
                        `LSR_MEMIO: begin


@@ -572,7 +570,7 @@ module Memory(
                                endcase
                end
                `DECODE_LDMSTM: if (!inbubble)
                                endcase
                end
                `DECODE_LDMSTM: if (!inbubble)

-                       if (lsr_state == `LSM_MEMIO)
+                       if (lsm_state == `LSM_MEMIO)

                                wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
                `DECODE_LDCSTC: begin end
                `DECODE_CDP: begin end
                                wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
                `DECODE_LDCSTC: begin end
                `DECODE_CDP: begin end


@@ -583,7 +581,7 @@ module Memory(
        
        /* LDM/STM register control logic. */
        always @(posedge clk)
        
        /* LDM/STM register control logic. */
        always @(posedge clk)

-               if (!rw_wait)
+               if (!rw_wait || lsm_state != `LSM_MEMIO)

                begin
                        prev_reg <= cur_reg;
                        regs <= next_regs;
                begin
                        prev_reg <= cur_reg;
                        regs <= next_regs;


@@ -591,6 +589,7 @@ module Memory(
        
        always @(*)
        begin
        
        always @(*)
        begin

+               st_read = 4'hx;

                offset = prev_offset;
                cur_reg = prev_reg;
                next_regs = regs;
                offset = prev_offset;
                cur_reg = prev_reg;
                next_regs = regs;


@@ -686,7 +685,6 @@ module Memory(
        
        always @(*)
        begin
        
        always @(*)
        begin

-               st_read = 4'hx;

                do_rd_data_latch = 0;
                
                next_outbubble = inbubble;
                do_rd_data_latch = 0;
                
                next_outbubble = inbubble;