output reg cp_req,
input cp_ack,
input cp_busy,
- output cp_rnw, /* 1 = read from CP, 0 = write to CP */
+ output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
input [31:0] cp_read,
output reg [31:0] cp_write,
reg [3:0] next_regsel, cur_reg, prev_reg;
reg next_writeback;
- wire next_outbubble;
- wire next_write_reg;
- wire [3:0] next_write_num;
- wire [31:0] next_write_data;
+ reg next_outbubble;
+ reg next_write_reg;
+ reg [3:0] next_write_num;
+ reg [31:0] next_write_data;
reg [1:0] lsr_state = 2'b01, next_lsr_state;
reg [31:0] align_s1, align_s2, align_rddata;
next_outbubble = rw_wait;
outstall = rw_wait;
addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
- raddr = insn[24] ? op0 : addr; /* pre/post increment */
+ raddr = insn[24] ? addr : op0; /* pre/post increment */
busaddr = raddr;
/* rotate to correct position */
align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
next_write_reg = 1'b1;
next_write_num = insn[19:16];
next_write_data = addr;
- next_lsr_state = 2'b10;
+ next_lsr_state = 2'b01;
end
default: begin end
endcase