ICache, Fetch: Re-pipe things such that the icache now has a one-cycle latency. ...
[firearm.git] / Writeback.v
index b0e69cf..d0d4304 100644 (file)
@@ -9,6 +9,7 @@ module Writeback(
        
        input [31:0] cpsr,
        input [31:0] spsr,
+       input cpsrup,
        
        output reg regfile_write,
        output reg [3:0] regfile_write_reg,
@@ -23,13 +24,13 @@ module Writeback(
        reg [31:0] last_outcpsr = 0, last_outspsr = 0;
        
        always @(*)
-               if (inbubble)
+               if (inbubble || !cpsrup)
                        outcpsr = last_outcpsr;
                else
                        outcpsr = cpsr;
        
        always @(*)
-               if (inbubble)
+               if (inbubble || !cpsrup)
                        outspsr = last_outspsr;
                else
                        outspsr = spsr;
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