Memory: Fix bug in which multiplies would cause a HDATA access. Fix bug in which...

[firearm.git] / Memory.v

diff --git a/Memory.v b/Memory.v
index 2bab914d38470a31dd3a9de3cfe1e433c90166c2..c709e83f9bddd130c691f6ae56b6fb53f896e7d4 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -87,7 +87,8 @@ module Memory(
                out_write_data <= next_write_data;
                regs <= next_regs;
                prev_reg <= cur_reg;
-               prev_offset <= offset;
+               if (!rw_wait)
+                       prev_offset <= offset;
                prev_raddr <= raddr;
                outcpsr <= next_outcpsr;
                outspsr <= spsr;
@@ -150,6 +151,7 @@ module Memory(
                                        next_swp_state = 2'b10;
                                        next_swp_oldval = rd_data;
                                end
+                               $display("SWP: read stage");
                        end
                        2'b10: begin
                                wr_req = 1'b1;
@@ -159,10 +161,12 @@ module Memory(
                                next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
                                if(!rw_wait)
                                        next_swp_state = 2'b01;
+                               $display("SWP: write stage");
                        end
                        default: begin end
                        endcase
                end
+               `DECODE_ALU_MULT: begin end
                `DECODE_ALU_HDATA_REG,
                `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
                        next_outbubble = rw_wait;
@@ -206,6 +210,7 @@ module Memory(
                                        if(!rw_wait)
                                                next_lsrh_state = 2'b10;
                                end
+                               $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
                        end
                        2'b10: begin
                                next_write_reg = 1'b1;
@@ -232,14 +237,14 @@ module Memory(
                        data_size = insn[22] ? 3'b001 : 3'b100;
                        case(lsr_state)
                        2'b01: begin
-                               rd_req = insn[20];
-                               wr_req = ~insn[20];
-                               next_write_reg = 1'b1;
+                               rd_req = insn[20] /* L */;
+                               wr_req = ~insn[20] /* L */;
+                               next_write_reg = insn[20] /* L */;
                                next_write_num = insn[15:12];
-                               if(insn[20]) begin
+                               if(insn[20] /* L */) begin
                                        next_write_data = align_rddata;
                                end
-                               if(insn[21] | !insn[24]) begin
+                               if(insn[21] /* W */ | !insn[24] /* P */) begin
                                        outstall = 1'b1;
                                        if(!rw_wait)
                                                next_lsr_state = 2'b10;
@@ -349,10 +354,7 @@ module Memory(
                                        next_outcpsr = spsr;
                                end
 
-                               if (rw_wait)
-                                       offset = prev_offset;   /* whoops, do this one again */
-                               else
-                                       offset = prev_offset + 6'h4;
+                               offset = prev_offset + 6'h4;
                                offset_sel = insn[24] ? offset : prev_offset;
                                raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
                                if(insn[20]) begin