system: Wire up outcpsr and outspsr from Execute to Memory.

[firearm.git] / Decode.v

diff --git a/Decode.v b/Decode.v
index 359bbc0d61ae5abacbbc36fcfd256b85ba6fa0ea..90ac3d6a302d96a10081ca6a07fe7ee226d4b9b7 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -63,11 +63,12 @@ module Decode(
                `DECODE_BRANCH,                 /* Branch */
                `DECODE_LDCSTC,                 /* Coprocessor data transfer */
                `DECODE_CDP,                    /* Coprocessor data op */
-               `DECODE_MRCMCR,                 /* Coprocessor register transfer */
                `DECODE_SWI:                    /* SWI */
-                       rpc = inpc - 8;
+                       rpc = inpc + 8;
+               `DECODE_MRCMCR:                 /* Coprocessor register transfer */
+                       rpc = inpc + 12;
                `DECODE_ALU:                    /* ALU */
-                       rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
+                       rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
                default:                        /* X everything else out */
                        rpc = 32'hxxxxxxxx;
                endcase
@@ -171,6 +172,7 @@ module Decode(
                begin
                        read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
+                       read_2 = insn[15:12];
                        
                        op0_out = regs0;
                        if(insn[25]) begin
@@ -180,6 +182,7 @@ module Decode(
                                op1_out = shift_res;
                                carry_out = shift_cflag_out;
                        end
+                       op2_out = regs2;
                end
                `DECODE_LDMSTM:         /* Block data transfer */
                begin