Hit all with the integrate.

[firearm.git] / RegFile.v

diff --git a/RegFile.v b/RegFile.v
index a9699e9..730a620 100644 (file)
--- a/RegFile.v
+++ b/RegFile.v
@@ -6,8 +6,11 @@ module RegFile(
        output reg [31:0] rdata_1,
        input [3:0] read_2,
        output reg [31:0] rdata_2,
        output reg [31:0] rdata_1,
        input [3:0] read_2,
        output reg [31:0] rdata_2,

-       input [3:0] write,
-       input write_req,
+       input [3:0] read_3,
+       output reg [31:0] rdata_3,
+       output reg [31:0] spsr,
+       input write,
+       input [3:0] write_reg,

        input [31:0] write_data
        );
        
        input [31:0] write_data
        );
        


@@ -29,28 +32,35 @@ module RegFile(
                regfile[4'hC] = 32'h0000A000;
                regfile[4'hD] = 32'h00000A00;
                regfile[4'hE] = 32'h000000A0;
                regfile[4'hC] = 32'h0000A000;
                regfile[4'hD] = 32'h00000A00;
                regfile[4'hE] = 32'h000000A0;

-               regfile[4'hF] = 32'h0000000A;
+               regfile[4'hF] = 32'h00000000;   /* Start off claiming we are in user mode. */

        end
        
        always @(*)
        begin
        end
        
        always @(*)
        begin

-               if ((read_0 == write) && write_req)
+               if ((read_0 == write_reg) && write)

                        rdata_0 = write_data;
                else
                        rdata_0 = regfile[read_0];
                
                        rdata_0 = write_data;
                else
                        rdata_0 = regfile[read_0];
                

-               if ((read_1 == write) && write_req)
+               if ((read_1 == write_reg) && write)

                        rdata_1 = write_data;
                else
                        rdata_1 = regfile[read_1];
                
                        rdata_1 = write_data;
                else
                        rdata_1 = regfile[read_1];
                

-               if ((read_2 == write) && write_req)
+               if ((read_2 == write_reg) && write)

                        rdata_2 = write_data;
                else
                        rdata_2 = regfile[read_2];
                        rdata_2 = write_data;
                else
                        rdata_2 = regfile[read_2];

+
+               if ((read_3 == write_reg) && write)
+                       rdata_3 = write_data;
+               else
+                       rdata_3 = regfile[read_3];
+               
+               spsr = regfile[4'hF];

        end
        
        always @(posedge clk)
        end
        
        always @(posedge clk)

-               if (write_req)
-                       regfile[write] <= write_data;
+               if (write)
+                       regfile[write_reg] <= write_data;

 endmodule
 endmodule