system: Wire up outcpsr and outspsr from Execute to Memory.

[firearm.git] / RegFile.v

diff --git a/RegFile.v b/RegFile.v
index a9699e93ab3b49eda73685d48b155367652c8036..1e94174573cdbc82faac662c73fdc70de33e6189 100644 (file)
--- a/RegFile.v
+++ b/RegFile.v
@@ -6,6 +6,9 @@ module RegFile(
        output reg [31:0] rdata_1,
        input [3:0] read_2,
        output reg [31:0] rdata_2,
+       input [3:0] read_3,
+       output reg [31:0] rdata_3,
+       output reg [31:0] spsr,
        input [3:0] write,
        input write_req,
        input [31:0] write_data
@@ -29,7 +32,7 @@ module RegFile(
                regfile[4'hC] = 32'h0000A000;
                regfile[4'hD] = 32'h00000A00;
                regfile[4'hE] = 32'h000000A0;
-               regfile[4'hF] = 32'h0000000A;
+               regfile[4'hF] = 32'h00000000;   /* Start off claiming we are in user mode. */
        end
        
        always @(*)
@@ -48,6 +51,13 @@ module RegFile(
                        rdata_2 = write_data;
                else
                        rdata_2 = regfile[read_2];
+
+               if ((read_3 == write) && write_req)
+                       rdata_3 = write_data;
+               else
+                       rdata_3 = regfile[read_3];
+               
+               spsr = regfile[4'hF];
        end
        
        always @(posedge clk)