module Memory(
input clk,
input Nrst,
- input [31:0] pc,
- input [31:0] insn,
- input [31:0] base,
- input [31:0] offset,
/* bus interface */
output reg [31:0] busaddr,
/* regfile interface */
output reg [3:0] st_read,
input [31:0] st_data,
+
+ /* Coprocessor interface */
+ output reg cp_req,
+ input cp_ack,
+ input cp_busy,
+
+ /* stage inputs */
+ input inbubble,
+ input [31:0] pc,
+ input [31:0] insn,
+ input [31:0] op0,
+ input [31:0] op1,
+ input [31:0] op2,
+ input write_reg,
+ input [3:0] write_num,
+ input [31:0] write_data,
- /* writeback to base */
- output reg writeback,
- output reg [3:0] regsel,
- output reg [31:0] regdata,
-
- /* pc stuff */
+ /* outputs */
+ output reg outstall,
+ output reg outbubble,
output reg [31:0] outpc,
- output reg [31:0] newpc,
+ output reg [31:0] outinsn,
+ output reg out_write_reg = 1'b0,
+ output reg [3:0] out_write_num = 4'bxxxx,
+ output reg [31:0] out_write_data = 32'hxxxxxxxx
+ );
- /* stall */
- output outstall,
- output reg outbubble,
- output reg flush
-);
+ reg [31:0] addr, raddr, next_regdata;
+ reg [3:0] next_regsel, cur_reg, prev_reg;
+ reg next_writeback, next_notdone, next_inc_next;
+ reg [31:0] align_s1, align_s2, align_rddata;
+
+ wire next_outbubble;
+ wire next_write_reg;
+ wire [3:0] next_write_num;
+ wire [31:0] next_write_data;
+
+ reg [15:0] regs, next_regs;
+ reg started = 1'b0, next_started;
- reg [31:0] addr, raddr;
reg notdone = 1'b0;
reg inc_next = 1'b0;
- wire [31:0] align_s1, align_s2, align_rddata;
- assign outstall = rw_wait | notdone;
+
+ always @(posedge clk)
+ begin
+ outpc <= pc;
+ outinsn <= insn;
+ outbubble <= next_outbubble;
+ out_write_reg <= next_write_reg;
+ out_write_num <= next_write_num;
+ out_write_data <= next_write_data;
+ notdone <= next_notdone;
+ inc_next <= next_inc_next;
+ regs <= next_regs;
+ prev_reg <= cur_reg;
+ started <= next_started;
+ end
always @(*)
begin
wr_data = 32'hxxxxxxxx;
busaddr = 32'hxxxxxxxx;
outstall = 1'b0;
+ next_notdone = 1'b0;
+ next_write_reg = write_reg;
+ next_write_num = write_num;
+ next_write_data = write_data;
+ next_inc_next = 1'b0;
+ next_outbubble = inbubble;
+ outstall = 1'b0;
+ next_regs = 16'b0;
+ next_started = started;
+ cp_req = 1'b0;
+
casez(insn)
`DECODE_LDRSTR_UNDEFINED: begin end
`DECODE_LDRSTR: begin
- addr = insn[23] ? base + offset : base - offset; /* up/down select */
- raddr = insn[24] ? base : addr;
- busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
- rd_req = insn[20];
- wr_req = ~insn[20];
- if(!insn[20]) begin /* store */
- st_read = insn[15:12];
- wr_data = insn[22] ? {4{st_data[7:0]}} : st_data;
+ if (!inbubble) begin
+ next_outbubble = rw_wait;
+ outstall = rw_wait | notdone;
+
+ addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+ raddr = insn[24] ? op0 : addr; /* pre/post increment */
+ busaddr = {raddr[31:2], 2'b0};
+ rd_req = insn[20];
+ wr_req = ~insn[20];
+
+ /* rotate to correct position */
+ align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+ align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+ /* select byte or word */
+ align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+
+ if(!insn[20]) begin
+ wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
+ end
+ else if(!inc_next) begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[15:12];
+ next_write_data = align_rddata;
+ next_inc_next = 1'b1;
+ end
+ else if(insn[21]) begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[19:16];
+ next_write_data = addr;
+ end
+ next_notdone = rw_wait & insn[20] & insn[21];
end
- else if(insn[15:12] == 4'hF)
- flush = 1'b1;
end
`DECODE_LDMSTM: begin
- end
- default: begin end
- endcase
- end
-
- assign align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
- assign align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
- assign align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
-
- always @(posedge clk)
- begin
- outpc <= pc;
- outbubble <= rw_wait;
- casez(insn)
- `DECODE_LDRSTR_UNDEFINED: begin
- writeback <= 1'b0;
- regsel <= 4'hx;
- regdata <= 32'hxxxxxxxx;
- notdone <= 1'b0;
- end
- `DECODE_LDRSTR: begin
- if(insn[20] && !inc_next) begin /* load - delegate regfile write to writeback stage */
- if(insn[15:12] == 4'hF) begin
- newpc <= align_rddata;
- end
- else begin
- writeback <= 1'b1;
- regsel <= insn[15:12];
- regdata <= align_rddata;
+ rd_req = insn[20];
+ wr_req = ~insn[20];
+ if(!started) begin
+ next_regs = op1[15:0];
+ next_started = 1'b1;
+ end
+ else if(inc_next) begin
+ if(insn[21]) begin
+ next_write_reg = 1'b1;
+ next_write_num = insn[19:16];
+ next_write_data = op0;
end
- inc_next <= 1'b1;
+ next_started = 1'b0;
end
- else if(insn[21]) begin /* write back */
- writeback <= 1'b1;
- regsel <= insn[19:16];
- regdata <= addr;
- inc_next <= 1'b0;
- end else begin
- writeback <= 1'b0;
- inc_next <= 1'b0;
- regsel <= 4'hx;
- regdata <= 32'hxxxxxxxx;
+ else if(rw_wait) begin
+ next_regs = regs;
+ cur_reg = prev_reg;
+ end
+ else begin
+ casez(regs)
+ 16'b???????????????1: begin
+ cur_reg = 4'h0;
+ next_regs = regs & 16'b1111111111111110;
+ end
+ 16'b??????????????10: begin
+ cur_reg = 4'h1;
+ next_regs = regs & 16'b1111111111111100;
+ end
+ 16'b?????????????100: begin
+ cur_reg = 4'h2;
+ next_regs = regs & 16'b1111111111111000;
+ end
+ 16'b????????????1000: begin
+ cur_reg = 4'h3;
+ next_regs = regs & 16'b1111111111110000;
+ end
+ 16'b???????????10000: begin
+ cur_reg = 4'h4;
+ next_regs = regs & 16'b1111111111100000;
+ end
+ 16'b??????????100000: begin
+ cur_reg = 4'h5;
+ next_regs = regs & 16'b1111111111000000;
+ end
+ 16'b?????????1000000: begin
+ cur_reg = 4'h6;
+ next_regs = regs & 16'b1111111110000000;
+ end
+ 16'b????????10000000: begin
+ cur_reg = 4'h7;
+ next_regs = regs & 16'b1111111100000000;
+ end
+ 16'b???????100000000: begin
+ cur_reg = 4'h8;
+ next_regs = regs & 16'b1111111000000000;
+ end
+ 16'b??????1000000000: begin
+ cur_reg = 4'h9;
+ next_regs = regs & 16'b1111110000000000;
+ end
+ 16'b?????10000000000: begin
+ cur_reg = 4'hA;
+ next_regs = regs & 16'b1111100000000000;
+ end
+ 16'b????100000000000: begin
+ cur_reg = 4'hB;
+ next_regs = regs & 16'b1111000000000000;
+ end
+ 16'b???1000000000000: begin
+ cur_reg = 4'hC;
+ next_regs = regs & 16'b1110000000000000;
+ end
+ 16'b??10000000000000: begin
+ cur_reg = 4'hD;
+ next_regs = regs & 16'b1100000000000000;
+ end
+ 16'b?100000000000000: begin
+ cur_reg = 4'hE;
+ next_regs = regs & 16'b1000000000000000;
+ end
+ 16'b1000000000000000: begin
+ cur_reg = 4'hF;
+ next_regs = 16'b0;
+ end
+ default: begin
+ cur_reg = 4'hx;
+ next_regs = 16'b0;
+ end
+ endcase
+ next_inc_next = next_regs == 16'b0;
+ next_notdone = ~next_inc_next | (rw_wait & insn[20] & insn[21]);
end
- notdone <= rw_wait & insn[20] & insn[21];
- end
- `DECODE_LDMSTM: begin
- end
- default: begin
- writeback <= 1'b0;
- regsel <= 4'hx;
- regdata <= 32'hxxxxxxxx;
- notdone <= 1'b0;
end
+ default: begin end
endcase
end
-
endmodule
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