Fetch: Fix async reset to actually not do it wrong.

[firearm.git] / ICache.v

diff --git a/ICache.v b/ICache.v
index e90f430930a6b554b09a4bc32247eed61517facd..e6754b722acb93829811c7758d64914ecbc538b2 100644 (file)
--- a/ICache.v
+++ b/ICache.v
@@ -32,7 +32,7 @@ module ICache(
        reg [21:0] cache_tags [15:0];
        reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
        
-       reg [4:0] i;
+       integer i;
        initial
                for (i = 0; i < 16; i = i + 1)
                begin
@@ -48,10 +48,11 @@ module ICache(
        reg [31:0] prev_rd_addr = 32'hFFFFFFFF;
        
        wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
-       
-       always @(*) begin       /* XXX does this work nowadays? */
+
+       wire [31:0] curdata = cache_data[rd_idx][rd_didx_word];
+       always @(*) begin
                rd_wait = rd_req && !cache_hit;
-               rd_data = cache_data[rd_idx][rd_didx_word];
+               rd_data = curdata;
        end
        
        reg [3:0] cache_fill_pos = 0;