tests/testbench: Add miniblarg. Put ldm_bonehead in a place where it will not get...

[firearm.git] / Decode.v

diff --git a/Decode.v b/Decode.v
index b54104601f4dd8560b1c51bc37dbc683bf9a6e37..2c227460eba0b046d3a0689f9b75da6835c6558a 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -2,6 +2,7 @@
 
 module Decode(
        input clk,
+       input stall,
        input [31:0] insn,
        input [31:0] inpc,
        input [31:0] incpsr,
@@ -139,16 +140,20 @@ module Decode(
                begin
                        read_0 = insn[19:16];
                        read_1 = insn[3:0];
-                       
+                       read_2 = insn[15:12];
+
                        op0_out = regs0;
                        op1_out = regs1;
+                       op2_out = regs2;
                end
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin
                        read_0 = insn[19:16];
+                       read_1 = insn[15:12];
                        
                        op0_out = regs0;
                        op1_out = {24'b0, insn[11:8], insn[3:0]};
+                       op2_out = regs1;
                end
                `DECODE_ALU:            /* ALU */
                begin
@@ -176,7 +181,7 @@ module Decode(
                        read_2 = insn[15:12];
                        
                        op0_out = regs0;
-                       if(insn[25]) begin
+                       if(!insn[25] /* immediate */) begin
                                op1_out = {20'b0, insn[11:0]};
                                carry_out = incpsr[`CPSR_C];
                        end else begin
@@ -222,12 +227,15 @@ module Decode(
 
        
        always @ (posedge clk) begin
-               op0 <= op0_out;   /* Rn - always */
-               op1 <= op1_out; /* 'operand 2' - Rm */
-               op2 <= op2_out;   /* thirdedge - Rs */
-               carry <= carry_out;
-               outcpsr <= incpsr;
-               outspsr <= inspsr;
+               if (!stall)
+               begin
+                       op0 <= op0_out;   /* Rn - always */
+                       op1 <= op1_out; /* 'operand 2' - Rm */
+                       op2 <= op2_out;   /* thirdedge - Rs */
+                       carry <= carry_out;
+                       outcpsr <= incpsr;
+                       outspsr <= inspsr;
+               end
        end
 
 endmodule