+ `LSM_BASEWB: begin end
+ `LSM_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDCSTC: begin end
+ `DECODE_CDP: begin end
+ `DECODE_MRCMCR: begin end
+ default: begin end
+ endcase
+ end
+
+ /* Bus data control logic. */
+ always @(*)
+ begin
+ wr_data = 32'hxxxxxxxx;
+
+ casez(insn)
+ `DECODE_ALU_SWP: if(!inbubble)
+ if (swp_state == `SWP_WRITING)
+ wr_data = insn[22] ? {4{op1[7:0]}} : op1;
+ `DECODE_ALU_MULT: begin end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!inbubble)
+ case(insn[6:5])
+ 2'b01: /* unsigned half */
+ wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
+ 2'b10: /* signed byte */
+ wr_data = {4{op2[7:0]}};
+ 2'b11: /* signed half */
+ wr_data = {2{op2[15:0]}};
+ default: begin end
+ endcase
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!inbubble) begin
+ wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
+ if (lsr_state == `LSR_STRB_WR)
+ case (busaddr[1:0])
+ 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
+ 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
+ 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
+ 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
+ endcase
+ end
+ `DECODE_LDMSTM: if (!inbubble)
+ if (lsm_state == `LSM_MEMIO)
+ wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
+ `DECODE_LDCSTC: begin end
+ `DECODE_CDP: begin end
+ `DECODE_MRCMCR: begin end
+ default: begin end
+ endcase
+ end
+
+ /* LDM/STM register control logic. */
+ always @(posedge clk)
+ if (!rw_wait || lsm_state != `LSM_MEMIO)
+ begin
+ prev_reg <= cur_reg;
+ regs <= next_regs;
+ end
+
+ always @(*)
+ begin
+ st_read = 4'hx;
+ offset = prev_offset;
+ cur_reg = prev_reg;
+ next_regs = regs;
+
+ casez(insn)
+ `DECODE_LDMSTM: if(!inbubble) begin
+ case(lsm_state)
+ `LSM_SETUP:
+ next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
+ op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
+ `LSM_MEMIO: begin
+ casez(regs)
+ 16'b???????????????1: begin
+ cur_reg = 4'h0;
+ next_regs = {regs[15:1], 1'b0};
+ end
+ 16'b??????????????10: begin
+ cur_reg = 4'h1;
+ next_regs = {regs[15:2], 2'b0};
+ end
+ 16'b?????????????100: begin
+ cur_reg = 4'h2;
+ next_regs = {regs[15:3], 3'b0};
+ end
+ 16'b????????????1000: begin
+ cur_reg = 4'h3;
+ next_regs = {regs[15:4], 4'b0};
+ end
+ 16'b???????????10000: begin
+ cur_reg = 4'h4;
+ next_regs = {regs[15:5], 5'b0};
+ end
+ 16'b??????????100000: begin
+ cur_reg = 4'h5;
+ next_regs = {regs[15:6], 6'b0};
+ end
+ 16'b?????????1000000: begin
+ cur_reg = 4'h6;
+ next_regs = {regs[15:7], 7'b0};
+ end
+ 16'b????????10000000: begin
+ cur_reg = 4'h7;
+ next_regs = {regs[15:8], 8'b0};
+ end
+ 16'b???????100000000: begin
+ cur_reg = 4'h8;
+ next_regs = {regs[15:9], 9'b0};
+ end
+ 16'b??????1000000000: begin
+ cur_reg = 4'h9;
+ next_regs = {regs[15:10], 10'b0};
+ end
+ 16'b?????10000000000: begin
+ cur_reg = 4'hA;
+ next_regs = {regs[15:11], 11'b0};
+ end
+ 16'b????100000000000: begin
+ cur_reg = 4'hB;
+ next_regs = {regs[15:12], 12'b0};
+ end
+ 16'b???1000000000000: begin
+ cur_reg = 4'hC;
+ next_regs = {regs[15:13], 13'b0};
+ end
+ 16'b??10000000000000: begin
+ cur_reg = 4'hD;
+ next_regs = {regs[15:14], 14'b0};
+ end
+ 16'b?100000000000000: begin
+ cur_reg = 4'hE;
+ next_regs = {regs[15], 15'b0};
+ end
+ 16'b1000000000000000: begin
+ cur_reg = 4'hF;
+ next_regs = 16'b0;
+ end
+ default: begin
+ cur_reg = 4'hx;
+ next_regs = 16'b0;
+ end
+ endcase
+ cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
+
+ st_read = cur_reg;
+ end
+ `LSM_BASEWB: begin end
+ `LSM_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ endcase
+ end
+
+ always @(*)
+ begin
+ do_rd_data_latch = 0;
+
+ next_outbubble = inbubble;
+
+ lsrh_rddata = 32'hxxxxxxxx;
+ lsrh_rddata_s1 = 16'hxxxx;
+ lsrh_rddata_s2 = 8'hxx;
+ next_swp_oldval = swp_oldval;
+
+ /* XXX shit not given about endianness */
+ casez(insn)
+ `DECODE_ALU_SWP: if(!inbubble) begin
+ next_outbubble = rw_wait;
+ case(swp_state)
+ `SWP_READING:
+ if(!rw_wait)
+ next_swp_oldval = rd_data;
+ `SWP_WRITING: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_ALU_MULT: begin end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
+ next_outbubble = rw_wait;
+
+ /* rotate to correct position */
+ case(insn[6:5])
+ 2'b01: begin /* unsigned half */
+ lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
+ end
+ 2'b10: begin /* signed byte */
+ lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
+ lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
+ lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
+ end
+ 2'b11: begin /* signed half */
+ lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
+ end
+ default: begin
+ lsrh_rddata = 32'hxxxxxxxx;
+ end
+ endcase
+
+ case(lsrh_state)
+ `LSRH_MEMIO: begin end
+ `LSRH_BASEWB:
+ next_outbubble = 1'b0;
+ `LSRH_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!inbubble) begin
+ next_outbubble = rw_wait;
+ /* rotate to correct position */
+ align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+ align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+ /* select byte or word */
+ align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+ case(lsr_state)
+ `LSR_MEMIO:
+ if (insn[22] /* B */ && !insn[20] /* L */)
+ do_rd_data_latch = 1;
+ `LSR_STRB_WR: begin end
+ `LSR_BASEWB:
+ next_outbubble = 0;
+ `LSR_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
+ `DECODE_LDMSTM: if(!inbubble) begin
+ next_outbubble = rw_wait;
+ case(lsm_state)
+ `LSM_SETUP: begin end
+ `LSM_MEMIO: begin end
+ `LSM_BASEWB:
+ next_outbubble = 0;
+ `LSM_WBFLUSH: begin end
+ default: $stop;
+ endcase
+ end
+ `DECODE_LDCSTC: begin end
+ `DECODE_CDP: if(!inbubble) begin