Wire in Memory. Fix small bug in Memory involving registers never ever getting outpu...

[firearm.git] / Memory.v

diff --git a/Memory.v b/Memory.v
index 9c010e71d98e5fe215af482fbe2ce53f45036814..e10a2e7b8bc611147839d5a5ead12889b63995bd 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -20,8 +20,9 @@ module Memory(
        input inbubble,
        input [31:0] pc,
        input [31:0] insn,
-       input [31:0] base,
-       input [31:0] offset,
+       input [31:0] op0,
+       input [31:0] op1,
+       input [31:0] op2,
        input write_reg,
        input [3:0] write_num,
        input [31:0] write_data,
@@ -36,15 +37,17 @@ module Memory(
        output reg [31:0] out_write_data = 32'hxxxxxxxx
        );
 
-       reg [31:0] addr, raddr, next_regdata;
-       reg [3:0] next_regsel;
-       reg next_writeback, next_notdone, next_inc_next;
+       reg [31:0] addr, raddr;
+       reg next_notdone, next_inc_next;
        reg [31:0] align_s1, align_s2, align_rddata;
-       
+
+       wire next_outbubble;    
        wire next_write_reg;
        wire [3:0] next_write_num;
        wire [31:0] next_write_data;
 
+       reg [15:0] regs, next_regs;
+
        reg notdone = 1'b0;
        reg inc_next = 1'b0;
 
@@ -52,12 +55,13 @@ module Memory(
        begin
                outpc <= pc;
                outinsn <= insn;
-               outbubble <= rw_wait;
-               out_write_reg <= next_writeback;
-               out_write_num <= next_regsel;
-               out_write_data <= next_regdata;
+               outbubble <= next_outbubble;
+               out_write_reg <= next_write_reg;
+               out_write_num <= next_write_num;
+               out_write_data <= next_write_data;
                notdone <= next_notdone;
                inc_next <= next_inc_next;
+               regs <= next_regs;
        end
 
        always @(*)
@@ -74,17 +78,19 @@ module Memory(
                next_write_num = write_num;
                next_write_data = write_data;
                next_inc_next = 1'b0;
+               next_outbubble = inbubble;
                outstall = 1'b0;
                
                casez(insn)
                `DECODE_LDRSTR_UNDEFINED: begin end
                `DECODE_LDRSTR: begin
                        if (!inbubble) begin
+                               next_outbubble = rw_wait;
                                outstall = rw_wait | notdone;
                        
-                               addr = insn[23] ? base + offset : base - offset; /* up/down select */
-                               raddr = insn[24] ? base : addr;
-                               busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
+                               addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+                               raddr = insn[24] ? op0 : addr; /* pre/post increment */
+                               busaddr = {raddr[31:2], 2'b0};
                                rd_req = insn[20];
                                wr_req = ~insn[20];
                                
@@ -95,8 +101,7 @@ module Memory(
                                align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
                                
                                if(!insn[20]) begin
-                                       st_read = insn[15:12];
-                                       wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
+                                       wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
                                end
                                else if(!inc_next) begin
                                        next_write_reg = 1'b1;
@@ -113,6 +118,47 @@ module Memory(
                        end
                end
                `DECODE_LDMSTM: begin
+                       busaddr = {op0[31:2], 2'b0};
+                       rd_req = insn[20];
+                       wr_req = ~insn[20];
+                       casez(regs)
+                       16'b???????????????1: begin
+                               next_regs = regs;
+                       end
+                       16'b??????????????10: begin
+                       end
+                       16'b?????????????100: begin
+                       end
+                       16'b????????????1000: begin
+                       end
+                       16'b???????????10000: begin
+                       end
+                       16'b??????????100000: begin
+                       end
+                       16'b?????????1000000: begin
+                       end
+                       16'b????????10000000: begin
+                       end
+                       16'b???????100000000: begin
+                       end
+                       16'b??????1000000000: begin
+                       end
+                       16'b?????10000000000: begin
+                       end
+                       16'b????100000000000: begin
+                       end
+                       16'b???1000000000000: begin
+                       end
+                       16'b??10000000000000: begin
+                       end
+                       16'b?100000000000000: begin
+                       end
+                       16'b1000000000000000: begin
+                       end
+                       default: begin
+                               next_inc_next = 1'b1;
+                       end
+                       endcase
                end
                default: begin end
                endcase