input inbubble,
input [31:0] pc,
input [31:0] insn,
- input [31:0] base,
- input [31:0] offset,
+ input [31:0] op0,
+ input [31:0] op1,
+ input [31:0] op2,
input write_reg,
input [3:0] write_num,
input [31:0] write_data,
wire [3:0] next_write_num;
wire [31:0] next_write_data;
+ reg [15:0] regs, next_regs;
+
reg notdone = 1'b0;
reg inc_next = 1'b0;
out_write_data <= next_regdata;
notdone <= next_notdone;
inc_next <= next_inc_next;
+ regs <= next_regs;
end
always @(*)
next_write_data = write_data;
next_inc_next = 1'b0;
outstall = 1'b0;
-
+ next_regs = 16'b0;
+
casez(insn)
`DECODE_LDRSTR_UNDEFINED: begin end
`DECODE_LDRSTR: begin
if (!inbubble) begin
outstall = rw_wait | notdone;
- addr = insn[23] ? base + offset : base - offset; /* up/down select */
- raddr = insn[24] ? base : addr;
- busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
+ addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+ raddr = insn[24] ? op0 : addr; /* pre/post increment */
+ busaddr = {raddr[31:2], 2'b0};
rd_req = insn[20];
wr_req = ~insn[20];
align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
if(!insn[20]) begin
- st_read = insn[15:12];
- wr_data = insn[22] ? {4{st_data[7:0]}} : st_data; /* XXX need to actually store just a byte */
+ wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
end
else if(!inc_next) begin
next_write_reg = 1'b1;
end
end
`DECODE_LDMSTM: begin
+ busaddr = {op0[31:2], 2'b0};
+ rd_req = insn[20];
+ wr_req = ~insn[20];
+ if(inc_next) begin
+ end
+ else if(rw_wait)
+ next_regs = regs;
+ else begin
+ casez(regs)
+ 16'b???????????????1: begin
+ next_regs = regs & 16'b1111111111111110;
+ end
+ 16'b??????????????10: begin
+ next_regs = regs & 16'b1111111111111100;
+ end
+ 16'b?????????????100: begin
+ next_regs = regs & 16'b1111111111111000;
+ end
+ 16'b????????????1000: begin
+ next_regs = regs & 16'b1111111111110000;
+ end
+ 16'b???????????10000: begin
+ next_regs = regs & 16'b1111111111100000;
+ end
+ 16'b??????????100000: begin
+ next_regs = regs & 16'b1111111111000000;
+ end
+ 16'b?????????1000000: begin
+ next_regs = regs & 16'b1111111110000000;
+ end
+ 16'b????????10000000: begin
+ next_regs = regs & 16'b1111111100000000;
+ end
+ 16'b???????100000000: begin
+ next_regs = regs & 16'b1111111000000000;
+ end
+ 16'b??????1000000000: begin
+ next_regs = regs & 16'b1111110000000000;
+ end
+ 16'b?????10000000000: begin
+ next_regs = regs & 16'b1111100000000000;
+ end
+ 16'b????100000000000: begin
+ next_regs = regs & 16'b1111000000000000;
+ end
+ 16'b???1000000000000: begin
+ next_regs = regs & 16'b1110000000000000;
+ end
+ 16'b??10000000000000: begin
+ next_regs = regs & 16'b1100000000000000;
+ end
+ 16'b?100000000000000: begin
+ next_regs = regs & 16'b1000000000000000;
+ end
+ 16'b1000000000000000: begin
+ next_regs = 16'b0;
+ end
+ default: begin
+ end
+ endcase
+ next_inc_next = next_regs == 16'b0;
+ next_notdone = ~next_inc_next;
+ end
end
default: begin end
endcase