input clk,
input Nrst,
+ input flush,
+
/* bus interface */
output reg [31:0] busaddr,
output reg rd_req,
output reg cp_req,
input cp_ack,
input cp_busy,
- output cp_rnw, /* 1 = read from CP, 0 = write to CP */
+ output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
input [31:0] cp_read,
output reg [31:0] cp_write,
output reg out_write_reg = 1'b0,
output reg [3:0] out_write_num = 4'bxxxx,
output reg [31:0] out_write_data = 32'hxxxxxxxx,
- output reg [31:0] out_spsr = 32'hxxxxxxxx,
- output reg [31:0] out_cpsr = 32'hxxxxxxxx
+ output reg [31:0] outspsr = 32'hxxxxxxxx,
+ output reg [31:0] outcpsr = 32'hxxxxxxxx
);
reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
reg [3:0] next_regsel, cur_reg, prev_reg;
reg next_writeback;
- wire next_outbubble;
- wire next_write_reg;
- wire [3:0] next_write_num;
- wire [31:0] next_write_data;
+ reg next_outbubble;
+ reg next_write_reg;
+ reg [3:0] next_write_num;
+ reg [31:0] next_write_data;
reg [1:0] lsr_state = 2'b01, next_lsr_state;
reg [31:0] align_s1, align_s2, align_rddata;
prev_reg <= cur_reg;
prev_offset <= offset;
prev_raddr <= raddr;
- out_cpsr <= next_outcpsr;
- out_spsr <= spsr;
+ outcpsr <= next_outcpsr;
+ outspsr <= spsr;
swp_state <= next_swp_state;
lsm_state <= next_lsm_state;
lsr_state <= next_lsr_state;
cp_rnw = 1'bx;
cp_write = 32'hxxxxxxxx;
offset = prev_offset;
- next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
+ next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
lsrh_rddata = 32'hxxxxxxxx;
lsrh_rddata_s1 = 16'hxxxx;
lsrh_rddata_s2 = 8'hxx;
cur_reg = prev_reg;
/* XXX shit not given about endianness */
- casez(insn)
+ if (flush)
+ next_outbubble = 1'b1;
+ else casez(insn)
`DECODE_ALU_SWP: if(!inbubble) begin
outstall = rw_wait;
next_outbubble = rw_wait;
next_outbubble = rw_wait;
outstall = rw_wait;
addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
- raddr = insn[24] ? op0 : addr; /* pre/post increment */
+ raddr = insn[24] ? addr : op0; /* pre/post increment */
busaddr = raddr;
/* rotate to correct position */
align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
next_write_reg = 1'b1;
next_write_num = insn[19:16];
next_write_data = addr;
- next_lsr_state = 2'b10;
+ next_lsr_state = 2'b01;
end
default: begin end
endcase
3'b001: begin
// next_regs = insn[23] ? op1[15:0] : op1[0:15];
/** verilator can suck my dick */
- next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
- op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
+ $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
+ next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
+ op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
offset = 6'b0;
outstall = 1'b1;
next_lsm_state = 3'b010;
next_regs = 16'b0;
end
endcase
- cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
+ cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
if(cur_reg == 4'hF && insn[22]) begin
next_outcpsr = spsr;
end
end
st_read = cur_reg;
- wr_data = st_data;
+ wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
busaddr = raddr;
+
+ $display("LDMSTM: Stage 2: Writing: reg %d, wr_data %08x, addr %08x", cur_reg, wr_data, busaddr);
outstall = 1'b1;
end
end
3'b100: begin
- next_write_reg = 1'b1;
+ next_write_reg = insn[21] /* writeback */;
next_write_num = insn[19:16];
next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
next_lsm_state = 3'b001;
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