Hit all with the integrate.

[firearm.git] / Decode.v

diff --git a/Decode.v b/Decode.v
index 6cfe08be37527214c09388a90167fdf0a2373b49..b54104601f4dd8560b1c51bc37dbc683bf9a6e37 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -5,10 +5,13 @@ module Decode(
        input [31:0] insn,
        input [31:0] inpc,
        input [31:0] incpsr,
        input [31:0] insn,
        input [31:0] inpc,
        input [31:0] incpsr,

+       input [31:0] inspsr,

        output reg [31:0] op0,
        output reg [31:0] op1,
        output reg [31:0] op2,
        output reg carry,
        output reg [31:0] op0,
        output reg [31:0] op1,
        output reg [31:0] op2,
        output reg carry,

+       output reg [31:0] outcpsr,
+       output reg [31:0] outspsr,

 
        output reg [3:0] read_0,
        output reg [3:0] read_1,
 
        output reg [3:0] read_0,
        output reg [3:0] read_1,


@@ -61,11 +64,12 @@ module Decode(
                `DECODE_BRANCH,                 /* Branch */
                `DECODE_LDCSTC,                 /* Coprocessor data transfer */
                `DECODE_CDP,                    /* Coprocessor data op */
                `DECODE_BRANCH,                 /* Branch */
                `DECODE_LDCSTC,                 /* Coprocessor data transfer */
                `DECODE_CDP,                    /* Coprocessor data op */

-               `DECODE_MRCMCR,                 /* Coprocessor register transfer */

                `DECODE_SWI:                    /* SWI */
                `DECODE_SWI:                    /* SWI */

-                       rpc = inpc - 8;
+                       rpc = inpc + 8;
+               `DECODE_MRCMCR:                 /* Coprocessor register transfer */
+                       rpc = inpc + 12;

                `DECODE_ALU:                    /* ALU */
                `DECODE_ALU:                    /* ALU */

-                       rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
+                       rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));

                default:                        /* X everything else out */
                        rpc = 32'hxxxxxxxx;
                endcase
                default:                        /* X everything else out */
                        rpc = 32'hxxxxxxxx;
                endcase


@@ -169,6 +173,7 @@ module Decode(
                begin
                        read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */
                begin
                        read_0 = insn[19:16]; /* Rn */
                        read_1 = insn[3:0];   /* Rm */

+                       read_2 = insn[15:12];

                        
                        op0_out = regs0;
                        if(insn[25]) begin
                        
                        op0_out = regs0;
                        if(insn[25]) begin


@@ -178,6 +183,7 @@ module Decode(
                                op1_out = shift_res;
                                carry_out = shift_cflag_out;
                        end
                                op1_out = shift_res;
                                carry_out = shift_cflag_out;
                        end

+                       op2_out = regs2;

                end
                `DECODE_LDMSTM:         /* Block data transfer */
                begin
                end
                `DECODE_LDMSTM:         /* Block data transfer */
                begin


@@ -220,6 +226,8 @@ module Decode(
                op1 <= op1_out; /* 'operand 2' - Rm */
                op2 <= op2_out;   /* thirdedge - Rs */
                carry <= carry_out;
                op1 <= op1_out; /* 'operand 2' - Rm */
                op2 <= op2_out;   /* thirdedge - Rs */
                carry <= carry_out;

+               outcpsr <= incpsr;
+               outspsr <= inspsr;

        end
 
 endmodule
        end
 
 endmodule