Deal with at least one case of A in decode by moving rpc out to its own case statemen...

[firearm.git] / Decode.v

diff --git a/Decode.v b/Decode.v
index 85aefbf7ac646d7ffc9e14b59af64a3731df710d..f38ca0d814461fd33986f22d799b513955be1dfd 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -1,6 +1,8 @@
+`include "ARM_Constants.v"
+

 module Decode(
        input clk,
 module Decode(
        input clk,

-       input [31:0] ansn,
+       input [31:0] insn,

        input [31:0] inpc,
        input [31:0] cps_in,
        output reg [31:0] op0,
        input [31:0] inpc,
        input [31:0] cps_in,
        output reg [31:0] op0,


@@ -28,128 +30,138 @@ module Decode(
        assign regs1 = (regsel1 == 4'b1111) ? rpc : iregs1;
        assign regs2 = iregs2; /* use regs2 for things that cannot be r15 */
 
        assign regs1 = (regsel1 == 4'b1111) ? rpc : iregs1;
        assign regs2 = iregs2; /* use regs2 for things that cannot be r15 */
 

-       IHATEARMSHIFT(.insn(ansn),
-                     .operand(regs1),
-                     .reg_amt(regs2),
-                     .cflag_in(cps_in[`COND_CBIT]),
-                     .res(shift_res),
-                     .cflag_out(shift_cflag));
+       IHATEARMSHIFT blowme(.insn(insn),
+                            .operand(regs1),
+                            .reg_amt(regs2),
+                            .cflag_in(cps_in[`CPSR_C]),
+                            .res(shift_res),
+                            .cflag_out(shift_cflag_out));
+       
+       always @(*)
+               casez (insn)
+               32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+//             32'b????00001???????????????1001????,   /* Multiply long */
+               32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
+               32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
+               32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
+               32'b????00010?00????????00001001????,   /* Atomic swap */
+               32'b????000100101111111111110001????,   /* Branch */
+               32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
+               32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
+               32'b????011????????????????????1????,   /* Undefined. I hate ARM */
+               32'b????01??????????????????????????,   /* Single data transfer */
+               32'b????100?????????????????????????,   /* Block data transfer */
+               32'b????101?????????????????????????,   /* Branch */
+               32'b????110?????????????????????????,   /* Coprocessor data transfer */
+               32'b????1110???????????????????0????,   /* Coprocessor data op */
+               32'b????1110???????????????????1????,   /* Coprocessor register transfer */
+               32'b????1111????????????????????????:   /* SWI */
+                       rpc = inpc - 8;
+               32'b????00??????????????????????????:   /* ALU */
+                       rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
+               default:                                /* X everything else out */
+                       rpc = 32'hxxxxxxxx;
+               endcase

 
        always @ (*) begin
 
        always @ (*) begin

-               casez (ansn)
+               casez (insn)

                32'b????000000??????????????1001????: begin /* Multiply */
                32'b????000000??????????????1001????: begin /* Multiply */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[15:12]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
-                       regsel2 = ansn[11:8];  /* Rs */
+                       regsel0 = insn[15:12]; /* Rn */
+                       regsel1 = insn[3:0];   /* Rm */
+                       regsel2 = insn[11:8];  /* Rs */

                        op1_res = regs1;
                        new_cps = cps_in;
                end
 /*
                32'b????00001???????????????1001????: begin * Multiply long *
                        op1_res = regs1;
                        new_cps = cps_in;
                end
 /*
                32'b????00001???????????????1001????: begin * Multiply long *

-                       regsel0 = ansn[11:8]; * Rn *
-                       regsel1 = ansn[3:0];  * Rm *
+                       regsel0 = insn[11:8]; * Rn *
+                       regsel1 = insn[3:0];  * Rm *

                        regsel2 = 4'b0;       * anyus *
                        op1_res = regs1;
                end
 */
                32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
                        regsel2 = 4'b0;       * anyus *
                        op1_res = regs1;
                end
 */
                32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */

-                       rpc = inpc - 8;

                        new_cps = cps_in;
                end
                32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
                        new_cps = cps_in;
                end
                32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */

-                       rpc = inpc - 8;

                        new_cps = cps_in;
                end
                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
                        new_cps = cps_in;
                end
                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */

-                       rpc = inpc - 8;

                        new_cps = cps_in;
                 end
                32'b????00??????????????????????????: begin /* ALU */
                        new_cps = cps_in;
                 end
                32'b????00??????????????????????????: begin /* ALU */

-                       rpc = inpc - (ansn[25] ? 8 : (ansn[4] ? 12 : 8));
-                       regsel0 = ansn[19:16]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
-                       regsel2 = ansn[11:8];  /* Rs for shift */
-                       if(ansn[25]) begin     /* the constant case */
+                       regsel0 = insn[19:16]; /* Rn */
+                       regsel1 = insn[3:0];   /* Rm */
+                       regsel2 = insn[11:8];  /* Rs for shift */
+                       if(insn[25]) begin     /* the constant case */

                                new_cps = cps_in;
                                new_cps = cps_in;

-                               op1_res = ({24'b0, ansn[7:0]} >> {ansn[11:8], 1'b0}) | ({24'b0, ansn[7:0]} << (5'b0 - {ansn[11:8], 1'b0}));
+                               op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));

                        end else begin
                        end else begin

-                               new_cps = {shift_cflag_out, cps_in[30:0]};
+                               new_cps = {cps_in[31:30], shift_cflag_out, cps_in[28:0]};

                                op1_res = shift_res;
                        end
                end
                32'b????00010?00????????00001001????: begin /* Atomic swap */
                                op1_res = shift_res;
                        end
                end
                32'b????00010?00????????00001001????: begin /* Atomic swap */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
+                       regsel0 = insn[19:16]; /* Rn */
+                       regsel1 = insn[3:0];   /* Rm */

                        regsel2 = 4'b0;        /* anyus */
                        op1_res = regs1;
                end
                32'b????000100101111111111110001????: begin /* Branch and exchange */
                        regsel2 = 4'b0;        /* anyus */
                        op1_res = regs1;
                end
                32'b????000100101111111111110001????: begin /* Branch and exchange */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[3:0];   /* Rn */
+                       regsel0 = insn[3:0];   /* Rn */

                        new_cps = cps_in;
                end
                32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
                        new_cps = cps_in;
                end
                32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       regsel1 = ansn[3:0];
+                       regsel0 = insn[19:16];
+                       regsel1 = insn[3:0];

                        regsel2 = 4'b0;
                        op1_res = regs1;
                        new_cps = cps_in;
                end
                32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
                        regsel2 = 4'b0;
                        op1_res = regs1;
                        new_cps = cps_in;
                end
                32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       regsel1 = ansn[3:0];
-                       op1_res = {24'b0, ansn[11:8], ansn[3:0]};
+                       regsel0 = insn[19:16];
+                       regsel1 = insn[3:0];
+                       op1_res = {24'b0, insn[11:8], insn[3:0]};

                        new_cps = cps_in;
                end
                32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
                        /* eat shit */
                end
                32'b????01??????????????????????????: begin /* Single data transfer */
                        new_cps = cps_in;
                end
                32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
                        /* eat shit */
                end
                32'b????01??????????????????????????: begin /* Single data transfer */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
-                       if(ansn[25]) begin
-                               op1_res = {20'b0, ansn[11:0]};
+                       regsel0 = insn[19:16]; /* Rn */
+                       regsel1 = insn[3:0];   /* Rm */
+                       if(insn[25]) begin
+                               op1_res = {20'b0, insn[11:0]};

                                new_cps = cps_in;
                        end else begin
                                op1_res = shift_res;
                                new_cps = cps_in;
                        end else begin
                                op1_res = shift_res;

-                               new_cps = shift_cflag_out;
+                               new_cps = {cps_in[31:30], shift_cflag_out, cps_in[28:0]};

                        end
                end
                32'b????100?????????????????????????: begin /* Block data transfer */
                        end
                end
                32'b????100?????????????????????????: begin /* Block data transfer */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       op1_res = {16'b0, ansn[15:0]};
+                       regsel0 = insn[19:16];
+                       op1_res = {16'b0, insn[15:0]};

                        new_cps = cps_in;
                end
                32'b????101?????????????????????????: begin /* Branch */
                        new_cps = cps_in;
                end
                32'b????101?????????????????????????: begin /* Branch */

-                       rpc = inpc - 8;
-                       op1_res = {6{ansn[23]}, ansn[23:0], 2'b0};
+                       op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};

                        new_cps = cps_in;
                end
                32'b????110?????????????????????????: begin /* Coprocessor data transfer */
                        new_cps = cps_in;
                end
                32'b????110?????????????????????????: begin /* Coprocessor data transfer */

-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       op1_res = {24'b0, ansn[7:0]};
+                       regsel0 = insn[19:16];
+                       op1_res = {24'b0, insn[7:0]};

                        new_cps = cps_in;
                end
                32'b????1110???????????????????0????: begin /* Coprocessor data op */
                        new_cps = cps_in;
                end
                32'b????1110???????????????????0????: begin /* Coprocessor data op */

-                       rpc = inpc - 8;

                        new_cps = cps_in;
                end
                32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
                        new_cps = cps_in;
                end
                32'b????1110???????????????????1????: begin /* Coprocessor register transfer */

-                       rpc = inpc - 8;

                        new_cps = cps_in;
                end
                32'b????1111????????????????????????: begin /* SWI */
                        new_cps = cps_in;
                end
                32'b????1111????????????????????????: begin /* SWI */

-                       rpc = inpc - 8;

                        new_cps = cps_in;
                end
                        new_cps = cps_in;
                end

-               default:
+               default: begin end

                endcase
        end
 
                endcase
        end
 


@@ -170,22 +182,21 @@ module IHATEARMSHIFT(
        output [31:0] res,
        output cflag_out
 );
        output [31:0] res,
        output cflag_out
 );

-       wire [1:0] shift_type;

        wire [5:0] shift_amt;
        wire elanus;
 
        wire [5:0] shift_amt;
        wire elanus;
 

-       shift_type = insn[6:5];
-       if(insn[4]) begin
-               shift_amt = {|reg_amt[7:5], reg_amt[4:0]};
-               elanus = 1'b1;
-       end else begin
-               shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
-               elanus = 1'b0;
-       end

 
        /* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */
        always @ (*) begin
 
        /* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */
        always @ (*) begin

-               case (shift_type)
+               if(insn[4]) begin
+                       shift_amt = {|reg_amt[7:5], reg_amt[4:0]};
+                       elanus = 1'b1;
+               end else begin
+                       shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
+                       elanus = 1'b0;
+               end
+
+               case (insn[6:5]) /* shift type */

                `SHIFT_LSL: begin
                        {cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
                end
                `SHIFT_LSL: begin
                        {cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
                end


@@ -199,7 +210,7 @@ module IHATEARMSHIFT(
                        if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
                                res = {cflag_in, operand[31:1]};
                                cflag_out = operand[0];
                        if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
                                res = {cflag_in, operand[31:1]};
                                cflag_out = operand[0];

-                       end else if(!shift_amt) begin
+                       end else if(shift_amt == 6'b0) begin

                                res = operand;
                                cflag_out = cflag_in;
                        end else begin
                                res = operand;
                                cflag_out = cflag_in;
                        end else begin


@@ -207,5 +218,6 @@ module IHATEARMSHIFT(
                                cflag_out = operand[shift_amt[4:0] - 5'b1];
                        end
                end
                                cflag_out = operand[shift_amt[4:0] - 5'b1];
                        end
                end

+               endcase

        end
 endmodule
        end
 endmodule