- always @ (*) begin
- casez (ansn)
- 32'b????000000??????????????1001????: begin /* Multiply */
- rpc = inpc - 8;
- regsel0 = ansn[15:12]; /* Rn */
- regsel1 = ansn[3:0]; /* Rm */
- regsel2 = ansn[11:8]; /* Rs */
- op1_res = regs1;
- new_cps = cps_in;
- end
-/*
- 32'b????00001???????????????1001????: begin * Multiply long *
- regsel0 = ansn[11:8]; * Rn *
- regsel1 = ansn[3:0]; * Rm *
- regsel2 = 4'b0; * anyus *
- op1_res = regs1;
- end
-*/
- 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
+ SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
+ .amt(insn[11:8]),
+ .res(rotate_res));
+
+ always @(*)
+ casez (insn)
+ `DECODE_ALU_MULT, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+// `DECODE_ALU_MUL_LONG, /* Multiply long */
+ `DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
+ `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
+ `DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
+ `DECODE_ALU_SWP, /* Atomic swap */
+ `DECODE_ALU_BX, /* Branch and exchange */
+ `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
+ `DECODE_ALU_HDATA_IMM, /* Halfword transfer - register offset */
+ `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
+ `DECODE_LDRSTR, /* Single data transfer */
+ `DECODE_LDMSTM, /* Block data transfer */
+ `DECODE_BRANCH, /* Branch */
+ `DECODE_LDCSTC, /* Coprocessor data transfer */
+ `DECODE_CDP, /* Coprocessor data op */
+ `DECODE_MRCMCR, /* Coprocessor register transfer */
+ `DECODE_SWI: /* SWI */