/* This module is mapped in physical memory from 0x00000000 to
* 0x00800000. rdata and ready must be driven to zero if the
- * address is not within the range of this module.
+ * address is not within the range of this module. There also
+ * exists a shadow up at 0x80000000.
*/
- wire decode = bus_addr[31:23] == 9'b0;
+ wire decode = bus_addr[30:23] == 8'b0;
wire [22:0] ramaddr = {bus_addr[22:2], 2'b0}; /* mask off lower two bits
* for word alignment */
reg [31:0] data [((8*1024*1024) / 4 - 1):0];
reg [31:0] temprdata = 0;
- reg [22:0] lastread = 23'h7FFFFFFF;
+ reg [22:0] lastread = 23'h7FFFFF;
assign bus_rdata = (bus_rd && decode) ? temprdata : 32'h0;
assign bus_ready = decode &&