Execute: fix rdiff

[firearm.git] / DCache.v

diff --git a/DCache.v b/DCache.v
index 472e1279df886e938d4ae77f2b24ab44ba22c2e8..edfcde194daa200d5b030da7825c6d7745b75423 100644 (file)
--- a/DCache.v
+++ b/DCache.v
@@ -51,6 +51,8 @@ module DCache(
        always @(*) begin
                rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
                rd_data = cache_data[idx][didx_word];
+               if (!rw_wait && rd_req)
+                       $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);
        end
        
        reg [3:0] cache_fill_pos = 0;
@@ -65,6 +67,7 @@ module DCache(
                        bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
                        bus_rd = 1;
                end else if (wr_req && bus_ack) begin
+                       $display("DCACHE: WRITE REQUEST: Addr %08x, data %08x, wait %d", addr, wr_data, rw_wait);
                        bus_addr = addr;
                        bus_wr = 1;
                        bus_wdata = wr_data;
@@ -76,7 +79,7 @@ module DCache(
                if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit))        /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
                        cache_fill_pos <= 0;
                else if (rd_req && !cache_hit) begin
-                       if (bus_ready) begin    /* Started the fill, and we have data. */
+                       if (bus_ready && bus_ack) begin /* Started the fill, and we have data. */
                                cache_data[idx][cache_fill_pos] <= bus_rdata;
                                cache_fill_pos <= cache_fill_pos + 1;
                                if (cache_fill_pos == 15) begin /* Done? */