Issue: Fix case in which lr is read in the instruction immediately after a bl; now...
[firearm.git] / ICache.v
index 8106259..d9fbf04 100644 (file)
--- a/ICache.v
+++ b/ICache.v
@@ -32,7 +32,7 @@ module ICache(
        reg [21:0] cache_tags [15:0];
        reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
        
-       reg [4:0] i;
+       integer i;
        initial
                for (i = 0; i < 16; i = i + 1)
                begin
@@ -70,14 +70,16 @@ module ICache(
                if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit))      /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
                        cache_fill_pos <= 0;
                else if (rd_req && !cache_hit) begin
-                       if (bus_ready) begin    /* Started the fill, and we have data. */
+                       if (bus_ack && bus_ready) begin /* Started the fill, and we have data. */
                                $display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
                                cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
                                cache_fill_pos <= cache_fill_pos + 1;
                                if (cache_fill_pos == 15) begin /* Done? */
                                        cache_tags[rd_idx] <= rd_tag;
                                        cache_valid[rd_idx] <= 1;
-                               end
+                                       $display("ICACHE: Fill complete for line %x, tag %x", rd_idx, rd_tag);
+                               end else
+                                       cache_valid[rd_idx] <= 0;
                        end
                end
        end
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