decode: stuff for halfword

[firearm.git] / Memory.v

diff --git a/Memory.v b/Memory.v
index 696b1a4090d8882ec609a8fcbc00a2c03e7f7d7f..33bd67492e2088e6d87a5dd3d2ead049307d40cc 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -11,6 +11,7 @@ module Memory(
        input rw_wait,
        output reg [31:0] wr_data,
        input [31:0] rd_data,
        input rw_wait,
        output reg [31:0] wr_data,
        input [31:0] rd_data,

+       output reg [2:0] data_size;

 
        /* regfile interface */
        output reg [3:0] st_read,
 
        /* regfile interface */
        output reg [3:0] st_read,


@@ -50,9 +51,9 @@ module Memory(
        );
 
        reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
        );
 
        reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;

+       reg [31:0] prevaddr;

        reg [3:0] next_regsel, cur_reg, prev_reg;
        reg next_writeback;
        reg [3:0] next_regsel, cur_reg, prev_reg;
        reg next_writeback;

-       reg [31:0] align_s1, align_s2, align_rddata;

 
        wire next_outbubble;    
        wire next_write_reg;
 
        wire next_outbubble;    
        wire next_write_reg;


@@ -60,6 +61,12 @@ module Memory(
        wire [31:0] next_write_data;
 
        reg [1:0] lsr_state = 2'b01, next_lsr_state;
        wire [31:0] next_write_data;
 
        reg [1:0] lsr_state = 2'b01, next_lsr_state;

+       reg [31:0] align_s1, align_s2, align_rddata;
+
+       reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
+       reg [31:0] lsrh_rddata;
+       reg [15:0] lsrh_rddata_s1;
+       reg [7:0] lsrh_rddata_s2;

 
        reg [15:0] regs, next_regs;
        reg [2:0] lsm_state = 3'b001, next_lsm_state;
 
        reg [15:0] regs, next_regs;
        reg [2:0] lsm_state = 3'b001, next_lsm_state;


@@ -83,41 +90,49 @@ module Memory(
                out_cpsr <= next_outcpsr;
                out_spsr <= spsr;
                swp_state <= next_swp_state;
                out_cpsr <= next_outcpsr;
                out_spsr <= spsr;
                swp_state <= next_swp_state;

+               lsm_state <= next_lsm_state;
+               lsr_state <= next_lsr_state;
+               lsrh_state <= next_lsrh_state;
+               prevaddr <= addr;

        end
 
        always @(*)
        begin
        end
 
        always @(*)
        begin

-               addr = 32'hxxxxxxxx;
+               addr = prevaddr;

                raddr = 32'hxxxxxxxx;
                rd_req = 1'b0;
                wr_req = 1'b0;
                wr_data = 32'hxxxxxxxx;
                busaddr = 32'hxxxxxxxx;
                raddr = 32'hxxxxxxxx;
                rd_req = 1'b0;
                wr_req = 1'b0;
                wr_data = 32'hxxxxxxxx;
                busaddr = 32'hxxxxxxxx;

+               data_size = 3'bxxx;

                outstall = 1'b0;
                next_write_reg = write_reg;
                next_write_num = write_num;
                next_write_data = write_data;
                next_outbubble = inbubble;
                outstall = 1'b0;
                next_write_reg = write_reg;
                next_write_num = write_num;
                next_write_data = write_data;
                next_outbubble = inbubble;

-               outstall = 1'b0;

                next_regs = regs;
                cp_req = 1'b0;
                cp_rnw = 1'bx;
                cp_write = 32'hxxxxxxxx;
                offset = prev_offset;
                next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
                next_regs = regs;
                cp_req = 1'b0;
                cp_rnw = 1'bx;
                cp_write = 32'hxxxxxxxx;
                offset = prev_offset;
                next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;

+               lsrh_rddata = 32'hxxxxxxxx;
+               lsrh_rddata_s1 = 32'hxxxxxxxx;
+               lsrh_rddata_s2 = 32'hxxxxxxxx;

                next_lsm_state = lsm_state;
                next_lsr_state = lsr_state;
                next_lsm_state = lsm_state;
                next_lsr_state = lsr_state;

+               next_lsrh_state = lsrh_state;

                next_swp_oldval = swp_oldval;
                next_swp_state = swp_state;
                cur_reg = prev_reg;
 
                /* XXX shit not given about endianness */
                next_swp_oldval = swp_oldval;
                next_swp_state = swp_state;
                cur_reg = prev_reg;
 
                /* XXX shit not given about endianness */

-               /* TODO ldrh/strh */

                casez(insn)
                `DECODE_ALU_SWP: if(!inbubble) begin
                        outstall = rw_wait;
                        next_outbubble = rw_wait;
                        busaddr = {op0[31:2], 2'b0};
                casez(insn)
                `DECODE_ALU_SWP: if(!inbubble) begin
                        outstall = rw_wait;
                        next_outbubble = rw_wait;
                        busaddr = {op0[31:2], 2'b0};

+                       data_size = insn[22] ? 3'b001 : 3'b100;

                        case(swp_state)
                        2'b01: begin
                                rd_req = 1'b1;
                        case(swp_state)
                        2'b01: begin
                                rd_req = 1'b1;


@@ -129,41 +144,93 @@ module Memory(
                        end
                        2'b10: begin
                                wr_req = 1'b1;
                        end
                        2'b10: begin
                                wr_req = 1'b1;

-                               wr_data = op1;
+                               wr_data = insn[22] ? {4{op1[7:0]}} : op1;

                                next_write_reg = 1'b1;
                                next_write_num = insn[15:12];
                                next_write_reg = 1'b1;
                                next_write_num = insn[15:12];

-                               next_write_data = swp_oldval;
+                               next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;

                                if(!rw_wait)
                                        next_swp_state = 2'b01;
                        end
                        default: begin end
                        endcase
                end
                                if(!rw_wait)
                                        next_swp_state = 2'b01;
                        end
                        default: begin end
                        endcase
                end

+               `DECODE_ALU_HDATA_REG,
+               `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
+                       next_outbubble = rw_wait;
+                       outstall = rw_wait;
+                       addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+                       raddr = insn[24] ? op0 : addr; /* pre/post increment */
+                       busaddr = raddr;
+                       /* rotate to correct position */
+                       case(insn[6:5])
+                       2'b00: begin end /* swp */
+                       2'b01: begin /* unsigned half */
+                               wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
+                               data_size = 3'b010;
+                               lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
+                       end
+                       2'b10: begin /* signed byte */
+                               wr_data = {4{op2[7:0]}};
+                               data_size = 3'b001;
+                               lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
+                               lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
+                               lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
+                       end
+                       2'b11: begin /* signed half */
+                               wr_data = {2{op2[15:0]}};
+                               data_size = 3'b010;
+                               lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
+                       end
+                       endcase
+
+                       case(lsrh_state)
+                       2'b01: begin
+                               rd_req = insn[20];
+                               wr_req = ~insn[20];
+                               next_write_num = insn[15:12];
+                               next_write_data = lsrh_rddata;
+                               if(insn[20]) begin
+                                       next_write_reg = 1'b1;
+                               end
+                               if(insn[21] | !insn[24]) begin
+                                       outstall = 1'b1;
+                                       if(!rw_wait)
+                                               next_lsrh_state = 2'b10;
+                               end
+                       end
+                       2'b10: begin
+                               next_write_reg = 1'b1;
+                               next_write_num = insn[19:16];
+                               next_write_data = addr;
+                               next_lsrh_state = 2'b10;
+                       end
+                       default: begin end
+                       endcase
+               end

                `DECODE_LDRSTR_UNDEFINED: begin end
                `DECODE_LDRSTR: if(!inbubble) begin
                        next_outbubble = rw_wait;
                        outstall = rw_wait;
                        addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
                        raddr = insn[24] ? op0 : addr; /* pre/post increment */
                `DECODE_LDRSTR_UNDEFINED: begin end
                `DECODE_LDRSTR: if(!inbubble) begin
                        next_outbubble = rw_wait;
                        outstall = rw_wait;
                        addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
                        raddr = insn[24] ? op0 : addr; /* pre/post increment */

-                       busaddr = {raddr[31:2], 2'b0};
-                               /* rotate to correct position */
+                       busaddr = raddr;
+                       /* rotate to correct position */

                        align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
                        align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
                        /* select byte or word */
                        align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
                        align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
                        align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
                        /* select byte or word */
                        align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;

-                       if(!insn[20]) begin
-                               wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
-                       end
+                       wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
+                       data_size = insn[22] ? 3'b001 : 3'b100;

                        case(lsr_state)
                        2'b01: begin
                                rd_req = insn[20];
                                wr_req = ~insn[20];
                        case(lsr_state)
                        2'b01: begin
                                rd_req = insn[20];
                                wr_req = ~insn[20];

+                               next_write_reg = 1'b1;
+                               next_write_num = insn[15:12];

                                if(insn[20]) begin
                                if(insn[20]) begin

-                                       next_write_reg = 1'b1;
-                                       next_write_num = insn[15:12];

                                        next_write_data = align_rddata;
                                end
                                        next_write_data = align_rddata;
                                end

-                                       if(insn[21]) begin
+                               if(insn[21] | !insn[24]) begin

                                        outstall = 1'b1;
                                        if(!rw_wait)
                                                next_lsr_state = 2'b10;
                                        outstall = 1'b1;
                                        if(!rw_wait)
                                                next_lsr_state = 2'b10;


@@ -182,6 +249,7 @@ module Memory(
                `DECODE_LDMSTM: if(!inbubble) begin
                        outstall = rw_wait;
                        next_outbubble = rw_wait;
                `DECODE_LDMSTM: if(!inbubble) begin
                        outstall = rw_wait;
                        next_outbubble = rw_wait;

+                       data_size = 3'b100;

                        case(lsm_state)
                        3'b001: begin
 //                             next_regs = insn[23] ? op1[15:0] : op1[0:15];
                        case(lsm_state)
                        3'b001: begin
 //                             next_regs = insn[23] ? op1[15:0] : op1[0:15];


@@ -288,7 +356,7 @@ module Memory(
 
                                st_read = cur_reg;
                                wr_data = st_data;
 
                                st_read = cur_reg;
                                wr_data = st_data;

-                               busaddr = {raddr[31:2], 2'b0};
+                               busaddr = raddr;

 
                                outstall = 1'b1;
 
 
                                outstall = 1'b1;