Ok, it work.

[firearm.git] / RegFile.v

diff --git a/RegFile.v b/RegFile.v
index f5a63aec68cc003ddf386a901cc13391f8d7d15e..95e5c71a2fba021725dae37c488dfc73f76867e1 100644 (file)
--- a/RegFile.v
+++ b/RegFile.v
@@ -6,6 +6,7 @@ module RegFile(
        output reg [31:0] rdata_1,
        input [3:0] read_2,
        output reg [31:0] rdata_2,
+       output reg [31:0] spsr,
        input [3:0] write,
        input write_req,
        input [31:0] write_data
@@ -22,14 +23,14 @@ module RegFile(
                regfile[4'h5] = 32'h00500000;
                regfile[4'h6] = 32'h05000000;
                regfile[4'h7] = 32'h50000000;
-               regfile[4'h8] = 32'h0000000A;
-               regfile[4'h9] = 32'h000000A0;
-               regfile[4'hA] = 32'h00000A00;
-               regfile[4'hB] = 32'h0000A000;
-               regfile[4'hC] = 32'h000A0000;
-               regfile[4'hD] = 32'h00A00000;
-               regfile[4'hE] = 32'h0A000000;
-               regfile[4'hF] = 32'hA0000000;
+               regfile[4'h8] = 32'hA0000000;
+               regfile[4'h9] = 32'h0A000000;
+               regfile[4'hA] = 32'h00A00000;
+               regfile[4'hB] = 32'h000A0000;
+               regfile[4'hC] = 32'h0000A000;
+               regfile[4'hD] = 32'h00000A00;
+               regfile[4'hE] = 32'h000000A0;
+               regfile[4'hF] = 32'h00000000;   /* Start off claiming we are in user mode. */
        end
        
        always @(*)
@@ -48,6 +49,8 @@ module RegFile(
                        rdata_2 = write_data;
                else
                        rdata_2 = regfile[read_2];
+               
+               spsr = regfile[4'hF];
        end
        
        always @(posedge clk)