Merge nyus:/storage/git/firearm

[firearm.git] / Decode.v

diff --git a/Decode.v b/Decode.v
index b58951abff823e5070d6c043d875438884c24502..9bfb03ddf9e63c6b3c21c6a4b7bbf735faf67136 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -10,6 +10,7 @@ module Decode(
        output reg [31:0] op1,
        output reg [31:0] op2,
        output reg carry,
+       output reg [31:0] outcpsr,
        output reg [31:0] outspsr,
 
        output reg [3:0] read_0,
@@ -63,9 +64,10 @@ module Decode(
                `DECODE_BRANCH,                 /* Branch */
                `DECODE_LDCSTC,                 /* Coprocessor data transfer */
                `DECODE_CDP,                    /* Coprocessor data op */
-               `DECODE_MRCMCR,                 /* Coprocessor register transfer */
                `DECODE_SWI:                    /* SWI */
                        rpc = inpc + 8;
+               `DECODE_MRCMCR:                 /* Coprocessor register transfer */
+                       rpc = inpc + 12;
                `DECODE_ALU:                    /* ALU */
                        rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
                default:                        /* X everything else out */
@@ -137,16 +139,20 @@ module Decode(
                begin
                        read_0 = insn[19:16];
                        read_1 = insn[3:0];
-                       
+                       read_2 = insn[15:12];
+
                        op0_out = regs0;
                        op1_out = regs1;
+                       op2_out = regs2;
                end
                `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
                begin
                        read_0 = insn[19:16];
+                       read_1 = insn[15:12];
                        
                        op0_out = regs0;
                        op1_out = {24'b0, insn[11:8], insn[3:0]};
+                       op2_out = regs1;
                end
                `DECODE_ALU:            /* ALU */
                begin
@@ -224,6 +230,7 @@ module Decode(
                op1 <= op1_out; /* 'operand 2' - Rm */
                op2 <= op2_out;   /* thirdedge - Rs */
                carry <= carry_out;
+               outcpsr <= incpsr;
                outspsr <= inspsr;
        end