branch added

[firearm.git] / Execute.v

diff --git a/Execute.v b/Execute.v
index ac759bb8b69642a8938665d6c97a35c21fff50ab..34c62af6e3f05ffbaec4d9bff884ab30e84a3cc2 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -19,7 +19,9 @@ module Execute(
        output reg [31:0] outcpsr = 0,
        output reg write_reg = 1'bx,
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] outcpsr = 0,
        output reg write_reg = 1'bx,
        output reg [3:0] write_num = 4'bxxxx,

-       output reg [31:0] write_data = 32'hxxxxxxxx
+       output reg [31:0] write_data = 32'hxxxxxxxx,
+       output reg [31:0] outpc
+       output reg outflush

        );
        
        reg mult_start;
        );
        
        reg mult_start;


@@ -62,6 +64,10 @@ module Execute(
                end
        end
 
                end
        end
 

+       reg prevstall = 0;
+       always @(posedge clk)
+               prevstall <= outstall;
+

        always @(*)
        begin
                outstall = stall;
        always @(*)
        begin
                outstall = stall;


@@ -71,13 +77,34 @@ module Execute(
                next_write_num = 4'hx;
                next_write_data = 32'hxxxxxxxx;
        
                next_write_num = 4'hx;
                next_write_data = 32'hxxxxxxxx;
        

+               mult_start = 0;
+               mult_acc0 = 32'hxxxxxxxx;
+               mult_in0 = 32'hxxxxxxxx;
+               mult_in1 = 32'hxxxxxxxx;
+       

                alu_in0 = 32'hxxxxxxxx;
                alu_in1 = 32'hxxxxxxxx;
                alu_op = 4'hx;  /* hax! */
                alu_setflags = 1'bx;
                
                casez (insn)
                alu_in0 = 32'hxxxxxxxx;
                alu_in1 = 32'hxxxxxxxx;
                alu_op = 4'hx;  /* hax! */
                alu_setflags = 1'bx;
                
                casez (insn)

-               `DECODE_ALU_MULT,       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+               `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+               begin
+                       if (!prevstall && !inbubble)
+                       begin
+                               mult_start = 1;
+                               mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
+                               mult_in0 = op1 /* Rm */;
+                               mult_in1 = op2 /* Rs */;
+                               $display("New MUL instruction");
+                       end
+                       outstall = stall | ((!prevstall | !mult_done) && !inbubble);
+                       next_outbubble = inbubble | !mult_done | !prevstall;
+                       next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
+                       next_write_reg = 1;
+                       next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
+                       next_write_data = mult_result;
+               end

 //             `DECODE_ALU_MUL_LONG,   /* Multiply long */
                `DECODE_ALU_MRS,        /* MRS (Transfer PSR to register) */
                `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
 //             `DECODE_ALU_MUL_LONG,   /* Multiply long */
                `DECODE_ALU_MRS,        /* MRS (Transfer PSR to register) */
                `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */


@@ -104,8 +131,17 @@ module Execute(
                end
                `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
                `DECODE_LDRSTR,         /* Single data transfer */
                end
                `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
                `DECODE_LDRSTR,         /* Single data transfer */

-               `DECODE_LDMSTM,         /* Block data transfer */
-               `DECODE_BRANCH,         /* Branch */
+               `DECODE_LDMSTM:         /* Block data transfer */
+               begin end
+               `DECODE_BRANCH:
+               begin
+                       outpc = pc + op0;
+                       if(insn[24]) begin
+                               next_write_reg = 1;
+                               next_write_num = 4'hE; /* link register */
+                               next_write_data = pc + 32'h4;
+                       end
+               end                     /* Branch */

                `DECODE_LDCSTC,         /* Coprocessor data transfer */
                `DECODE_CDP,            /* Coprocessor data op */
                `DECODE_MRCMCR,         /* Coprocessor register transfer */
                `DECODE_LDCSTC,         /* Coprocessor data transfer */
                `DECODE_CDP,            /* Coprocessor data op */
                `DECODE_MRCMCR,         /* Coprocessor register transfer */


@@ -154,7 +190,6 @@ module Multiplier(
        end
 endmodule
 
        end
 endmodule
 

-/* XXX is the interface correct? */

 module ALU(
        input clk,
        input Nrst,     /* XXX not used yet */
 module ALU(
        input clk,
        input Nrst,     /* XXX not used yet */


@@ -173,12 +208,15 @@ module ALU(
        wire [31:0] res;
        wire flag_n, flag_z, flag_c, flag_v, setres;
        wire [32:0] sum, diff, rdiff;
        wire [31:0] res;
        wire flag_n, flag_z, flag_c, flag_v, setres;
        wire [32:0] sum, diff, rdiff;

+       wire sum_v, diff_v, rdiff_v;

 
        assign sum = {1'b0, in0} + {1'b0, in1};
        assign diff = {1'b0, in0} - {1'b0, in1};
        assign rdiff = {1'b0, in1} + {1'b0, in0};
 
        assign sum = {1'b0, in0} + {1'b0, in1};
        assign diff = {1'b0, in0} - {1'b0, in1};
        assign rdiff = {1'b0, in1} + {1'b0, in0};

+       assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
+       assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
+       assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);

 
 

-       /* TODO XXX flag_v not set correctly */

        always @(*) begin
                res = 32'hxxxxxxxx;
                setres = 1'bx;
        always @(*) begin
                res = 32'hxxxxxxxx;
                setres = 1'bx;


@@ -197,26 +235,32 @@ module ALU(
                end
                `ALU_SUB: begin
                        {flag_c, result} = diff;
                end
                `ALU_SUB: begin
                        {flag_c, result} = diff;

+                       flag_v = diff_v;

                        setres = 1'b1;
                end
                `ALU_RSB: begin
                        {flag_c, result} = rdiff;
                        setres = 1'b1;
                end
                `ALU_RSB: begin
                        {flag_c, result} = rdiff;

+                       flag_v = rdiff_v;

                        setres = 1'b1;
                end
                `ALU_ADD: begin
                        {flag_c, result} = sum;
                        setres = 1'b1;
                end
                `ALU_ADD: begin
                        {flag_c, result} = sum;

+                       flag_v = sum_v;

                        setres = 1'b1;
                end
                `ALU_ADC: begin
                        {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
                        setres = 1'b1;
                end
                `ALU_ADC: begin
                        {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};

+                       flag_v = sum_v | (~sum[31] & result[31]);

                        setres = 1'b1;
                end
                `ALU_SBC: begin
                        {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
                        setres = 1'b1;
                end
                `ALU_SBC: begin
                        {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};

+                       flag_v = diff_v | (diff[31] & ~result[31]);

                        setres = 1'b1;
                end
                `ALU_RSC: begin
                        {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
                        setres = 1'b1;
                end
                `ALU_RSC: begin
                        {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};

+                       flag_v = rdiff_v | (rdiff[31] & ~result[31]);

                        setres = 1'b1;
                end
                `ALU_TST: begin
                        setres = 1'b1;
                end
                `ALU_TST: begin


@@ -231,10 +275,12 @@ module ALU(
                end
                `ALU_CMP: begin
                        {flag_c, result} = diff;
                end
                `ALU_CMP: begin
                        {flag_c, result} = diff;

+                       flag_v = diff_v;

                        setres = 1'b0;
                end
                `ALU_CMN: begin
                        {flag_c, result} = sum;
                        setres = 1'b0;
                end
                `ALU_CMN: begin
                        {flag_c, result} = sum;

+                       flag_v = sum_v;

                        setres = 1'b0;
                end
                `ALU_ORR: begin
                        setres = 1'b0;
                end
                `ALU_ORR: begin