+ end
+ `LSRH_BASEWB: begin end
+ `LSRH_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!inbubble) begin
+ addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+ raddr = insn[24] ? addr : op0; /* pre/post increment */
+ busaddr = raddr;
+ wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
+ data_size = insn[22] ? 3'b001 : 3'b100;
+ case (lsr_state)
+ `LSR_MEMIO: begin
+ rd_req = insn[20] /* L */ || insn[22] /* B */;
+ wr_req = !insn[20] /* L */ && !insn[22]/* B */;
+ end
+ `LSR_STRB_WR:
+ wr_req = 1;
+ `LSR_BASEWB: begin end
+ `LSR_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDMSTM: if (!inbubble) begin
+ data_size = 3'b100;
+ case (lsm_state)
+ `LSM_SETUP:
+ offset = 6'b0;
+ `LSM_MEMIO: begin
+ rd_req = insn[20];
+ wr_req = ~insn[20];
+ offset = prev_offset + 6'h4;
+ offset_sel = insn[24] ? offset : prev_offset;
+ raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
+ busaddr = raddr;
+ end
+ `LSM_BASEWB: begin end
+ `LSM_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDCSTC: begin end
+ `DECODE_CDP: begin end
+ `DECODE_MRCMCR: begin end
+ default: begin end
+ endcase
+ end
+
+ /* Bus data control logic. */
+ always @(*)
+ begin
+ wr_data = 32'hxxxxxxxx;
+
+ casez(insn)
+ `DECODE_ALU_SWP: if(!inbubble)
+ if (swp_state == `SWP_WRITING)
+ wr_data = insn[22] ? {4{op1[7:0]}} : op1;
+ `DECODE_ALU_MULT: begin end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!inbubble)
+ case(insn[6:5])
+ 2'b01: /* unsigned half */
+ wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
+ 2'b10: /* signed byte */
+ wr_data = {4{op2[7:0]}};
+ 2'b11: /* signed half */
+ wr_data = {2{op2[15:0]}};
+ default: begin end
+ endcase
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!inbubble) begin
+ wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
+ if (lsr_state == `LSR_STRB_WR)
+ case (busaddr[1:0])
+ 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
+ 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
+ 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
+ 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
+ endcase
+ end
+ `DECODE_LDMSTM: if (!inbubble)
+ if (lsr_state == `LSM_MEMIO)
+ wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
+ `DECODE_LDCSTC: begin end
+ `DECODE_CDP: begin end
+ `DECODE_MRCMCR: begin end
+ default: begin end
+ endcase
+ end
+
+ /* LDM/STM register control logic. */
+ always @(posedge clk)
+ if (!rw_wait)
+ begin
+ prev_reg <= cur_reg;
+ regs <= next_regs;
+ end
+
+ always @(*)
+ begin
+ offset = prev_offset;
+ cur_reg = prev_reg;
+ next_regs = regs;
+
+ casez(insn)
+ `DECODE_LDMSTM: if(!inbubble) begin
+ case(lsm_state)
+ `LSM_SETUP:
+ next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
+ op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
+ `LSM_MEMIO: begin