Add testbench padded hex.

[firearm.git] / DCache.v

diff --git a/DCache.v b/DCache.v
index 4528bd8853144d4aebb3e9949b0e9e842a9b8e62..6ec26a730a8661e3a62f6414be2a257743fd9150 100644 (file)
--- a/DCache.v
+++ b/DCache.v
@@ -29,9 +29,9 @@ module DCache(
        
        reg cache_valid [15:0];
        reg [21:0] cache_tags [15:0];
-       reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
-       
-       reg [4:0] i;
+       reg [31:0] cache_data [255:0 /* {line,word} */];
+
+       integer i;      
        initial
                for (i = 0; i < 16; i = i + 1)
                begin
@@ -44,38 +44,53 @@ module DCache(
        wire [3:0] idx = addr[9:6];
        wire [21:0] tag = addr[31:10];
        
+       reg [31:0] prev_addr = 32'hFFFFFFFF;
+       
        wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
        
+       wire [31:0] curdata = cache_data[{idx,didx_word}];
        always @(*) begin
                rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
-               rd_data = cache_data[idx][didx_word];
+               rd_data = curdata;
+               if (!rw_wait && rd_req)
+                       $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);
        end
        
        reg [3:0] cache_fill_pos = 0;
        assign bus_req = (rd_req && !cache_hit) || wr_req;
        always @(*)
+       begin
+               bus_rd = 0;
+               bus_wr = 0;
+               bus_addr = 0;
+               bus_wdata = 0;
                if (rd_req && !cache_hit && bus_ack) begin
                        bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
                        bus_rd = 1;
                end else if (wr_req && bus_ack) begin
+                       $display("DCACHE: WRITE REQUEST: Addr %08x, data %08x", addr, wr_data);
                        bus_addr = addr;
                        bus_wr = 1;
                        bus_wdata = wr_data;
-               end else begin
-                       bus_addr = 0;
-                       bus_rd = 0;
                end
+       end
        
-       always @(posedge clk)
-               if (rd_req && !cache_hit) begin
-                       if (bus_ready) begin    /* Started the fill, and we have data. */
-                               cache_data[idx][cache_fill_pos] <= bus_rdata;
-                               cache_fill_pos <= cache_fill_pos + 1;
-                               if (cache_fill_pos == 15) begin /* Done? */
-                                       cache_tags[idx] <= tag;
-                                       cache_valid[idx] <= 1;
-                               end
-                       end
-               end else if (wr_req && cache_hit)
-                       cache_data[idx][addr[5:2]] = wr_data;
+       always @(posedge clk) begin
+               prev_addr <= {addr[31:6], 6'b0};
+               if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit))        /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
+                       cache_fill_pos <= 0;
+               else if (rd_req && !cache_hit && bus_ready && bus_ack) begin    /* Started the fill, and we have data. */
+                       $display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", addr, bus_addr, bus_rdata, bus_req, bus_ack);
+                       cache_fill_pos <= cache_fill_pos + 1;
+                       if (cache_fill_pos == 15) begin /* Done? */
+                               cache_tags[idx] <= tag;
+                               cache_valid[idx] <= 1;
+                       end else
+                               cache_valid[idx] <= 0;
+               end
+               
+               /* Split this out because XST is kind of silly about this sort of thing. */
+               if ((rd_req && !cache_hit && bus_ready && bus_ack) || (wr_req && cache_hit))
+                       cache_data[wr_req ? {idx,addr[5:2]} : {idx,cache_fill_pos}] <= wr_req ? wr_data : bus_rdata;
+       end
 endmodule