- if (rd_req && !cache_hit) begin
- bus_req = 1;
- if (bus_ack) begin
- bus_addr = {rd_addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
- bus_rd = 1;
- end
+ if (rd_req && !cache_hit && bus_ack) begin
+ bus_addr = {rd_addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
+ bus_rd = 1;