assign read_0 out

[firearm.git] / system.v

diff --git a/system.v b/system.v
index 1035489c237ac9185a351dd18e81d9a4c0418bef..de462cd83178dac386a1a720f629e711fb6c301e 100644 (file)
--- a/system.v
+++ b/system.v
@@ -8,9 +8,11 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
        wire [31:0] bus_wdata;
        wire bus_rd, bus_wr;
        wire bus_ready;
-       
-       wire bus_req_icache = bus_req[`BUS_ICACHE];
+
+       wire bus_req_icache;    
+       assign bus_req = {7'b0, bus_req_icache};
        wire bus_ack_icache = bus_ack[`BUS_ICACHE];
+       
        wire [31:0] bus_addr_icache;
        wire [31:0] bus_wdata_icache;
        wire bus_rd_icache;
@@ -30,6 +32,22 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
        wire icache_rd_req;
        wire icache_rd_wait;
        wire [31:0] icache_rd_data;
+       
+       wire stall_cause_issue;
+       
+       wire stall_in_fetch = stall_cause_issue;
+       wire stall_in_issue = 0;
+       
+       wire bubble_out_fetch;
+       wire bubble_out_issue;
+       wire [31:0] insn_out_fetch;
+       wire [31:0] insn_out_issue;
+       wire [31:0] pc_out_fetch;
+       wire [31:0] pc_out_issue;
+       
+       assign bubbleshield = bubble_out_issue;
+       assign insn = insn_out_issue;
+       assign pc = pc_out_issue;
 
        BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 
@@ -42,7 +60,7 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
                .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
                .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
                .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
-
+       
        BlockRAM blockram(
                .clk(clk),
                .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
@@ -54,7 +72,25 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
                .Nrst(1 /* XXX */),
                .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
                .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
-               .stall(0 /* XXX */), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
-               .bubble(bubbleshield), .insn(insn), .pc(pc));
-
+               .stall(stall_in_fetch), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
+               .bubble(bubble_out_fetch), .insn(insn_out_fetch),
+               .pc(pc_out_fetch));
+       
+       Issue issue(
+               .clk(clk),
+               .Nrst(1 /* XXX */),
+               .stall(stall_in_issue), .flush(0 /* XXX */),
+               .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
+               .inpc(pc_out_fetch), .cpsr(0 /* XXX */),
+               .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
+               .outpc(pc_out_issue), .outinsn(insn_out_issue));
+       
+       reg [31:0] clockno = 0;
+       always @(posedge clk)
+       begin
+               clockno <= clockno + 1;
+               $display("------------------------------------------------------------------------------");
+               $display("%3d: FETCH:           Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
+               $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
+       end
 endmodule