decode shift suck less

[firearm.git] / system.v

diff --git a/system.v b/system.v
index 251b43c348dd3d84e8ff14553e0ea2266014f563..fb28c4f47bead83b42e5cc8c38ce3436cbe4e2a7 100644 (file)
--- a/system.v
+++ b/system.v
@@ -38,7 +38,8 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
        wire stall_in_fetch = stall_cause_issue;
        wire stall_in_issue = 0;
        
-       wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_cpsr;
+       wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2;
+       wire decode_out_carry;
        wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
        wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2;
        
@@ -99,7 +100,7 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
                .clk(clk),
                .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(0 /* XXX */),
                .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
-               .outcpsr(decode_out_cpsr),
+               .carry(decode_out_carry),
                .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
                .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
        
@@ -110,6 +111,6 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
                $display("------------------------------------------------------------------------------");
                $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
                $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
-               $display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, cpsr %08x", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_cpsr);
+               $display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
        end
 endmodule