+ always @(posedge clk)
+ begin
+ if (start) begin
+ bitfield <= in0;
+ multiplicand <= in1;
+ acc <= acc0;
+ done <= 0;
+ end else begin
+ bitfield <= {2'b00, bitfield[31:2]};
+ multiplicand <= {multiplicand[29:0], 2'b00};
+ acc <= acc +
+ (bitfield[0] ? multiplicand : 0) +
+ (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
+ if (bitfield == 0) begin
+ result <= acc;
+ done <= 1;
+ end
+ end
+ end
+endmodule
+
+module ALU(
+ input clk,
+ input Nrst, /* XXX not used yet */
+
+ input [31:0] in0,
+ input [31:0] in1,
+ input [31:0] cpsr,
+ input [3:0] op,
+ input setflags,
+ input shifter_carry,
+
+ output reg [31:0] result,
+ output reg [31:0] cpsr_out,
+ output reg setres
+);
+ wire [31:0] res;
+ wire flag_n, flag_z, flag_c, flag_v, setres;
+ wire [32:0] sum, diff, rdiff;
+ wire sum_v, diff_v, rdiff_v;
+
+ assign sum = {1'b0, in0} + {1'b0, in1};
+ assign diff = {1'b0, in0} - {1'b0, in1};
+ assign rdiff = {1'b0, in1} + {1'b0, in0};
+ assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
+ assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
+ assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
+
+ always @(*) begin
+ res = 32'hxxxxxxxx;
+ setres = 1'bx;
+ flag_c = cpsr[`CPSR_C];
+ flag_v = cpsr[`CPSR_V];
+ case(op)
+ `ALU_AND: begin
+ result = in0 & in1;
+ flag_c = shifter_carry;
+ setres = 1'b1;
+ end
+ `ALU_EOR: begin
+ result = in0 ^ in1;
+ flag_c = shifter_carry;
+ setres = 1'b1;
+ end
+ `ALU_SUB: begin
+ {flag_c, result} = diff;
+ flag_v = diff_v;
+ setres = 1'b1;
+ end
+ `ALU_RSB: begin
+ {flag_c, result} = rdiff;
+ flag_v = rdiff_v;
+ setres = 1'b1;
+ end
+ `ALU_ADD: begin
+ {flag_c, result} = sum;
+ flag_v = sum_v;
+ setres = 1'b1;
+ end
+ `ALU_ADC: begin
+ {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
+ flag_v = sum_v | (~sum[31] & result[31]);
+ setres = 1'b1;
+ end
+ `ALU_SBC: begin
+ {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
+ flag_v = diff_v | (diff[31] & ~result[31]);
+ setres = 1'b1;
+ end
+ `ALU_RSC: begin
+ {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
+ flag_v = rdiff_v | (rdiff[31] & ~result[31]);
+ setres = 1'b1;
+ end
+ `ALU_TST: begin
+ result = in0 & in1;
+ flag_c = shifter_carry;
+ setres = 1'b0;
+ end
+ `ALU_TEQ: begin
+ result = in0 ^ in1;
+ flag_c = shifter_carry;
+ setres = 1'b0;
+ end
+ `ALU_CMP: begin
+ {flag_c, result} = diff;
+ flag_v = diff_v;
+ setres = 1'b0;
+ end
+ `ALU_CMN: begin
+ {flag_c, result} = sum;
+ flag_v = sum_v;
+ setres = 1'b0;
+ end
+ `ALU_ORR: begin
+ result = in0 | in1;
+ flag_c = shifter_carry;
+ setres = 1'b1;
+ end
+ `ALU_MOV: begin
+ result = in1;
+ flag_c = shifter_carry;
+ setres = 1'b1;
+ end
+ `ALU_BIC: begin
+ result = in0 & (~in1);
+ flag_c = shifter_carry;
+ setres = 1'b1;
+ end
+ `ALU_MVN: begin
+ result = ~in1;
+ flag_c = shifter_carry;
+ setres = 1'b1;
+ end
+ endcase
+
+ flag_z = (result == 0);
+ flag_n = result[31];
+
+ cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
+ end