+
+module SuckLessRotator(
+ input [31:0] oper,
+ input [3:0] amt,
+ output [31:0] res
+);
+
+ wire [31:0] stage1, stage2, stage3;
+ assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
+ assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
+ assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
+ assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
+
+endmodule