Decode: Fix stupid bug in which stalls did not stall the decoder.
[firearm.git] / Execute.v
index 34c62af..38a192f 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -9,6 +9,7 @@ module Execute(
        input [31:0] pc,
        input [31:0] insn,
        input [31:0] cpsr,
        input [31:0] pc,
        input [31:0] insn,
        input [31:0] cpsr,
+       input [31:0] spsr,
        input [31:0] op0,
        input [31:0] op1,
        input [31:0] op2,
        input [31:0] op0,
        input [31:0] op1,
        input [31:0] op2,
@@ -17,11 +18,15 @@ module Execute(
        output reg outstall = 0,
        output reg outbubble = 1,
        output reg [31:0] outcpsr = 0,
        output reg outstall = 0,
        output reg outbubble = 1,
        output reg [31:0] outcpsr = 0,
+       output reg [31:0] outspsr = 0,
        output reg write_reg = 1'bx,
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] write_data = 32'hxxxxxxxx,
        output reg write_reg = 1'bx,
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] write_data = 32'hxxxxxxxx,
-       output reg [31:0] outpc
-       output reg outflush
+       output reg [31:0] jmppc,
+       output reg jmp,
+       output reg [31:0] outpc,
+       output reg [31:0] outinsn,
+       output reg [31:0] outop0, outop1, outop2
        );
        
        reg mult_start;
        );
        
        reg mult_start;
@@ -36,11 +41,12 @@ module Execute(
        wire alu_setres;
        
        reg next_outbubble;
        wire alu_setres;
        
        reg next_outbubble;
-       reg [31:0] next_outcpsr;
+       reg [31:0] next_outcpsr, next_outspsr;
        reg next_write_reg;
        reg [3:0] next_write_num;
        reg next_write_reg;
        reg [3:0] next_write_num;
+
        reg [31:0] next_write_data;
        reg [31:0] next_write_data;
-       
+
        Multiplier multiplier(
                .clk(clk), .Nrst(Nrst),
                .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
        Multiplier multiplier(
                .clk(clk), .Nrst(Nrst),
                .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
@@ -58,9 +64,15 @@ module Execute(
                begin
                        outbubble <= next_outbubble;
                        outcpsr <= next_outcpsr;
                begin
                        outbubble <= next_outbubble;
                        outcpsr <= next_outcpsr;
+                       outspsr <= next_outspsr;
                        write_reg <= next_write_reg;
                        write_num <= next_write_num;
                        write_data <= next_write_data;
                        write_reg <= next_write_reg;
                        write_num <= next_write_num;
                        write_data <= next_write_data;
+                       outpc <= pc;
+                       outinsn <= insn;
+                       outop0 <= op0;
+                       outop1 <= op1;
+                       outop2 <= op2;
                end
        end
 
                end
        end
 
@@ -71,22 +83,26 @@ module Execute(
        always @(*)
        begin
                outstall = stall;
        always @(*)
        begin
                outstall = stall;
-               next_outbubble = inbubble;
+               next_outbubble = inbubble | flush;
                next_outcpsr = cpsr;
                next_outcpsr = cpsr;
+               next_outspsr = spsr;
                next_write_reg = 0;
                next_write_num = 4'hx;
                next_write_data = 32'hxxxxxxxx;
                next_write_reg = 0;
                next_write_num = 4'hx;
                next_write_data = 32'hxxxxxxxx;
-       
+
                mult_start = 0;
                mult_acc0 = 32'hxxxxxxxx;
                mult_in0 = 32'hxxxxxxxx;
                mult_in1 = 32'hxxxxxxxx;
                mult_start = 0;
                mult_acc0 = 32'hxxxxxxxx;
                mult_in0 = 32'hxxxxxxxx;
                mult_in1 = 32'hxxxxxxxx;
-       
+
                alu_in0 = 32'hxxxxxxxx;
                alu_in1 = 32'hxxxxxxxx;
                alu_op = 4'hx;  /* hax! */
                alu_setflags = 1'bx;
                alu_in0 = 32'hxxxxxxxx;
                alu_in1 = 32'hxxxxxxxx;
                alu_op = 4'hx;  /* hax! */
                alu_setflags = 1'bx;
-               
+
+               jmp = 1'b0;
+               jmppc = 32'h00000000;
+
                casez (insn)
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
                casez (insn)
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
@@ -106,9 +122,29 @@ module Execute(
                        next_write_data = mult_result;
                end
 //             `DECODE_ALU_MUL_LONG,   /* Multiply long */
                        next_write_data = mult_result;
                end
 //             `DECODE_ALU_MUL_LONG,   /* Multiply long */
-               `DECODE_ALU_MRS,        /* MRS (Transfer PSR to register) */
+               `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
+               begin
+                       next_write_reg = 1;
+                       next_write_num = insn[15:12];
+                       if (insn[22] /* Ps */)
+                               next_write_data = spsr;
+                       else
+                               next_write_data = cpsr;
+               end
                `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
                `DECODE_ALU_MSR,        /* MSR (Transfer register to PSR) */
-               `DECODE_ALU_MSR_FLAGS,  /* MSR (Transfer register or immediate to PSR, flag bits only) */
+               `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
+                       if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))       /* flags only */
+                       begin
+                               if (insn[22] /* Ps */)
+                                       next_outspsr = {op0[31:29], spsr[28:0]};
+                               else
+                                       next_outcpsr = {op0[31:29], cpsr[28:0]};
+                       end else begin
+                               if (insn[22] /* Ps */)
+                                       next_outspsr = op0;
+                               else
+                                       next_outcpsr = op0;
+                       end
                `DECODE_ALU_SWP,        /* Atomic swap */
                `DECODE_ALU_BX,         /* Branch */
                `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
                `DECODE_ALU_SWP,        /* Atomic swap */
                `DECODE_ALU_BX,         /* Branch */
                `DECODE_ALU_HDATA_REG,  /* Halfword transfer - register offset */
@@ -119,7 +155,7 @@ module Execute(
                        alu_in0 = op0;
                        alu_in1 = op1;
                        alu_op = insn[24:21];
                        alu_in0 = op0;
                        alu_in1 = op1;
                        alu_op = insn[24:21];
-                       alu_setflags = insn[20] /* I */;
+                       alu_setflags = insn[20] /* S */;
                        
                        if (alu_setres) begin
                                next_write_reg = 1;
                        
                        if (alu_setres) begin
                                next_write_reg = 1;
@@ -127,7 +163,7 @@ module Execute(
                                next_write_data = alu_result;
                        end
                        
                                next_write_data = alu_result;
                        end
                        
-                       next_outcpsr = alu_outcpsr;
+                       next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
                end
                `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
                `DECODE_LDRSTR,         /* Single data transfer */
                end
                `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
                `DECODE_LDRSTR,         /* Single data transfer */
@@ -135,11 +171,14 @@ module Execute(
                begin end
                `DECODE_BRANCH:
                begin
                begin end
                `DECODE_BRANCH:
                begin
-                       outpc = pc + op0;
-                       if(insn[24]) begin
-                               next_write_reg = 1;
-                               next_write_num = 4'hE; /* link register */
-                               next_write_data = pc + 32'h4;
+                       if(!inbubble) begin
+                               jmppc = pc + op0 + 32'h8;
+                               if(insn[24]) begin
+                                       next_write_reg = 1;
+                                       next_write_num = 4'hE; /* link register */
+                                       next_write_data = pc - 32'h4;
+                               end
+                               jmp = 1'b1;
                        end
                end                     /* Branch */
                `DECODE_LDCSTC,         /* Coprocessor data transfer */
                        end
                end                     /* Branch */
                `DECODE_LDCSTC,         /* Coprocessor data transfer */
@@ -205,8 +244,8 @@ module ALU(
        output reg [31:0] cpsr_out,
        output reg setres
 );
        output reg [31:0] cpsr_out,
        output reg setres
 );
-       wire [31:0] res;
-       wire flag_n, flag_z, flag_c, flag_v, setres;
+       reg [31:0] res;
+       reg flag_n, flag_z, flag_c, flag_v;
        wire [32:0] sum, diff, rdiff;
        wire sum_v, diff_v, rdiff_v;
 
        wire [32:0] sum, diff, rdiff;
        wire sum_v, diff_v, rdiff_v;
 
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