Merge nyus:/storage/git/firearm

[firearm.git] / Memory.v

diff --git a/Memory.v b/Memory.v
index 33bd67492e2088e6d87a5dd3d2ead049307d40cc..eb4006f5884d3c71ccd7a5e20959a4238a2d4622 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -4,6 +4,8 @@ module Memory(
        input clk,
        input Nrst,
 
+       input flush,
+
        /* bus interface */
        output reg [31:0] busaddr,
        output reg rd_req,
@@ -11,7 +13,7 @@ module Memory(
        input rw_wait,
        output reg [31:0] wr_data,
        input [31:0] rd_data,
-       output reg [2:0] data_size;
+       output reg [2:0] data_size,
 
        /* regfile interface */
        output reg [3:0] st_read,
@@ -46,8 +48,8 @@ module Memory(
        output reg out_write_reg = 1'b0,
        output reg [3:0] out_write_num = 4'bxxxx,
        output reg [31:0] out_write_data = 32'hxxxxxxxx,
-       output reg [31:0] out_spsr = 32'hxxxxxxxx,
-       output reg [31:0] out_cpsr = 32'hxxxxxxxx
+       output reg [31:0] outspsr = 32'hxxxxxxxx,
+       output reg [31:0] outcpsr = 32'hxxxxxxxx
        );
 
        reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
@@ -87,8 +89,8 @@ module Memory(
                prev_reg <= cur_reg;
                prev_offset <= offset;
                prev_raddr <= raddr;
-               out_cpsr <= next_outcpsr;
-               out_spsr <= spsr;
+               outcpsr <= next_outcpsr;
+               outspsr <= spsr;
                swp_state <= next_swp_state;
                lsm_state <= next_lsm_state;
                lsr_state <= next_lsr_state;
@@ -115,10 +117,10 @@ module Memory(
                cp_rnw = 1'bx;
                cp_write = 32'hxxxxxxxx;
                offset = prev_offset;
-               next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
+               next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
                lsrh_rddata = 32'hxxxxxxxx;
-               lsrh_rddata_s1 = 32'hxxxxxxxx;
-               lsrh_rddata_s2 = 32'hxxxxxxxx;
+               lsrh_rddata_s1 = 16'hxxxx;
+               lsrh_rddata_s2 = 8'hxx;
                next_lsm_state = lsm_state;
                next_lsr_state = lsr_state;
                next_lsrh_state = lsrh_state;
@@ -127,7 +129,9 @@ module Memory(
                cur_reg = prev_reg;
 
                /* XXX shit not given about endianness */
-               casez(insn)
+               if (flush)
+                       next_outbubble = 1'b1;
+               else casez(insn)
                `DECODE_ALU_SWP: if(!inbubble) begin
                        outstall = rw_wait;
                        next_outbubble = rw_wait;