do some first pass Execute wiring

[firearm.git] / RegFile.v

diff --git a/RegFile.v b/RegFile.v
index 47f5024f6a60c25c957c5a9d974f2936b04992b9..f5a63aec68cc003ddf386a901cc13391f8d7d15e 100644 (file)
--- a/RegFile.v
+++ b/RegFile.v
@@ -1,11 +1,11 @@
 module RegFile(
        input clk,
+       input [3:0] read_0,
+       output reg [31:0] rdata_0,
        input [3:0] read_1,
        output reg [31:0] rdata_1,
        input [3:0] read_2,
        output reg [31:0] rdata_2,
-       input [3:0] read_3,
-       output reg [31:0] rdata_3,
        input [3:0] write,
        input write_req,
        input [31:0] write_data
@@ -34,6 +34,11 @@ module RegFile(
        
        always @(*)
        begin
+               if ((read_0 == write) && write_req)
+                       rdata_0 = write_data;
+               else
+                       rdata_0 = regfile[read_0];
+               
                if ((read_1 == write) && write_req)
                        rdata_1 = write_data;
                else
@@ -43,11 +48,6 @@ module RegFile(
                        rdata_2 = write_data;
                else
                        rdata_2 = regfile[read_2];
-               
-               if ((read_3 == write) && write_req)
-                       rdata_3 = write_data;
-               else
-                       rdata_3 = regfile[read_3];
        end
        
        always @(posedge clk)