Memory: Fix FSM for LDR/STR. Fix pre/post increment to be, uh, pre/post increment...

[firearm.git] / Issue.v

diff --git a/Issue.v b/Issue.v
index ef53bc3ed932365292c5969a7a95b7f74d88f42f..7b281a30016d8dc0254a3207678ae3b895a86a04 100644 (file)
--- a/Issue.v
+++ b/Issue.v
@@ -282,7 +282,7 @@ module Issue(
                waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
                waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
                
-               outstall = (waiting && !inbubble) || stall;     /* Happens in an always @*, because it is an exception. */
+               outstall = ((waiting && !inbubble) || stall) && !flush; /* Happens in an always @*, because it is an exception. */
        end
        
        /* Actually do the issue. */
@@ -297,6 +297,7 @@ module Issue(
                        cpsr_inflight[1] = 1'b0;
                        regs_inflight[0] = 16'b0;
                        regs_inflight[1] = 16'b0;
+                       outbubble <= 1'b1;
                end
                else if (!stall)
                begin
@@ -305,7 +306,7 @@ module Issue(
                        regs_inflight[0] <= regs_inflight[1];
                        regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
                        
-                       outbubble <= inbubble | waiting | !condition_met | flush;
+                       outbubble <= inbubble | waiting | !condition_met;
                        outpc <= inpc;
                        outinsn <= insn;
                end