Merge Memory.

[firearm.git] / Execute.v

diff --git a/Execute.v b/Execute.v
index cefc4ef00d2c0d23535f938e3c3e91494764e25b..cd71d7628e8004cc1ca8b003a0146684e8a55278 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -23,7 +23,9 @@ module Execute(
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] write_data = 32'hxxxxxxxx,
        output reg [31:0] jmppc,
-       output reg jmp
+       output reg jmp,
+       output reg [31:0] outpc,
+       output reg [31:0] outinsn
        );
        
        reg mult_start;
@@ -65,6 +67,8 @@ module Execute(
                        write_reg <= next_write_reg;
                        write_num <= next_write_num;
                        write_data <= next_write_data;
+                       outpc <= pc;
+                       outinsn <= insn;
                end
        end
 
@@ -163,13 +167,15 @@ module Execute(
                begin end
                `DECODE_BRANCH:
                begin
-                       jmppc = pc + op0 + 32'h8;
-                       if(insn[24]) begin
-                               next_write_reg = 1;
-                               next_write_num = 4'hE; /* link register */
-                               next_write_data = pc + 32'h4;
+                       if(!inbubble) begin
+                               jmppc = pc + op0 + 32'h8;
+                               if(insn[24]) begin
+                                       next_write_reg = 1;
+                                       next_write_num = 4'hE; /* link register */
+                                       next_write_data = pc - 32'h4;
+                               end
+                               jmp = 1'b1;
                        end
-                       jmp = 1'b1;
                end                     /* Branch */
                `DECODE_LDCSTC,         /* Coprocessor data transfer */
                `DECODE_CDP,            /* Coprocessor data op */
@@ -234,8 +240,8 @@ module ALU(
        output reg [31:0] cpsr_out,
        output reg setres
 );
-       wire [31:0] res;
-       wire flag_n, flag_z, flag_c, flag_v, setres;
+       reg [31:0] res;
+       reg flag_n, flag_z, flag_c, flag_v;
        wire [32:0] sum, diff, rdiff;
        wire sum_v, diff_v, rdiff_v;