tests: Add the new testbench.

[firearm.git] / DCache.v

diff --git a/DCache.v b/DCache.v
index e1d5d82f76e5cdede350878e347eac86ffb71843..a3484a7558b81e5bf3db42a4d11e3b0f2b834e5b 100644 (file)
--- a/DCache.v
+++ b/DCache.v
@@ -44,11 +44,15 @@ module DCache(
        wire [3:0] idx = addr[9:6];
        wire [21:0] tag = addr[31:10];
        
        wire [3:0] idx = addr[9:6];
        wire [21:0] tag = addr[31:10];
        

+       reg [31:0] prev_addr = 32'hFFFFFFFF;
+       

        wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
        
        always @(*) begin
                rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
                rd_data = cache_data[idx][didx_word];
        wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
        
        always @(*) begin
                rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
                rd_data = cache_data[idx][didx_word];

+               if (!rw_wait && rd_req)
+                       $display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);

        end
        
        reg [3:0] cache_fill_pos = 0;
        end
        
        reg [3:0] cache_fill_pos = 0;


@@ -63,14 +67,18 @@ module DCache(
                        bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
                        bus_rd = 1;
                end else if (wr_req && bus_ack) begin
                        bus_addr = {addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
                        bus_rd = 1;
                end else if (wr_req && bus_ack) begin

+                       $display("DCACHE: WRITE REQUEST: Addr %08x, data %08x, wait %d", addr, wr_data, rw_wait);

                        bus_addr = addr;
                        bus_wr = 1;
                        bus_wdata = wr_data;
                end
        end
        
                        bus_addr = addr;
                        bus_wr = 1;
                        bus_wdata = wr_data;
                end
        end
        

-       always @(posedge clk)
-               if (rd_req && !cache_hit) begin
+       always @(posedge clk) begin
+               prev_addr <= {addr[31:6], 6'b0};
+               if (rd_req && (cache_fill_pos != 0) && ((prev_addr != {addr[31:6], 6'b0}) || cache_hit))        /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
+                       cache_fill_pos <= 0;
+               else if (rd_req && !cache_hit) begin

                        if (bus_ready) begin    /* Started the fill, and we have data. */
                                cache_data[idx][cache_fill_pos] <= bus_rdata;
                                cache_fill_pos <= cache_fill_pos + 1;
                        if (bus_ready) begin    /* Started the fill, and we have data. */
                                cache_data[idx][cache_fill_pos] <= bus_rdata;
                                cache_fill_pos <= cache_fill_pos + 1;


@@ -81,4 +89,5 @@ module DCache(
                        end
                end else if (wr_req && cache_hit)
                        cache_data[idx][addr[5:2]] = wr_data;
                        end
                end else if (wr_req && cache_hit)
                        cache_data[idx][addr[5:2]] = wr_data;

+       end

 endmodule
 endmodule