Ok, A mitigated.

[firearm.git] / system.v

diff --git a/system.v b/system.v
index e33bbff1ede9eb05cfc1741006ce28a35b9e7169..afd7a177c989f80c058e83d3f1cfc51e04c7de10 100644 (file)
--- a/system.v
+++ b/system.v
@@ -84,4 +84,11 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
                .inpc(pc_out_fetch), .cpsr(0 /* XXX */),
                .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
                .outpc(pc_out_issue), .outinsn(insn_out_issue));
+       
+       always @(posedge clk)
+       begin
+               $display("Clock-time dump:");
+               $display("Fetch stage: Bubble output: %d, Instruction: %08x, PC: %08x", bubble_out_fetch, insn_out_fetch, pc_out_fetch);
+               $display("Issue stage: Stall output: %d, Bubble output: %d, Instruction: %08x, PC: %08x", stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
+       end
 endmodule