ram: Add a string printing test, WHICH WORKS!

[firearm.git] / Execute.v

diff --git a/Execute.v b/Execute.v
index 4c7b893487e9381ad0fcbfbc69885ee5c70b2081..38a192ff95f56fd3464915d0bb3bfc02e5bddaf4 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -22,8 +22,11 @@ module Execute(
        output reg write_reg = 1'bx,
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] write_data = 32'hxxxxxxxx,
        output reg write_reg = 1'bx,
        output reg [3:0] write_num = 4'bxxxx,
        output reg [31:0] write_data = 32'hxxxxxxxx,

-       output reg [31:0] outpc
-       output reg outflush
+       output reg [31:0] jmppc,
+       output reg jmp,
+       output reg [31:0] outpc,
+       output reg [31:0] outinsn,
+       output reg [31:0] outop0, outop1, outop2

        );
        
        reg mult_start;
        );
        
        reg mult_start;


@@ -41,8 +44,9 @@ module Execute(
        reg [31:0] next_outcpsr, next_outspsr;
        reg next_write_reg;
        reg [3:0] next_write_num;
        reg [31:0] next_outcpsr, next_outspsr;
        reg next_write_reg;
        reg [3:0] next_write_num;

+

        reg [31:0] next_write_data;
        reg [31:0] next_write_data;

-       
+

        Multiplier multiplier(
                .clk(clk), .Nrst(Nrst),
                .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
        Multiplier multiplier(
                .clk(clk), .Nrst(Nrst),
                .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),


@@ -64,6 +68,11 @@ module Execute(
                        write_reg <= next_write_reg;
                        write_num <= next_write_num;
                        write_data <= next_write_data;
                        write_reg <= next_write_reg;
                        write_num <= next_write_num;
                        write_data <= next_write_data;

+                       outpc <= pc;
+                       outinsn <= insn;
+                       outop0 <= op0;
+                       outop1 <= op1;
+                       outop2 <= op2;

                end
        end
 
                end
        end
 


@@ -74,23 +83,26 @@ module Execute(
        always @(*)
        begin
                outstall = stall;
        always @(*)
        begin
                outstall = stall;

-               next_outbubble = inbubble;
+               next_outbubble = inbubble | flush;

                next_outcpsr = cpsr;
                next_outspsr = spsr;
                next_write_reg = 0;
                next_write_num = 4'hx;
                next_write_data = 32'hxxxxxxxx;
                next_outcpsr = cpsr;
                next_outspsr = spsr;
                next_write_reg = 0;
                next_write_num = 4'hx;
                next_write_data = 32'hxxxxxxxx;

-       
+

                mult_start = 0;
                mult_acc0 = 32'hxxxxxxxx;
                mult_in0 = 32'hxxxxxxxx;
                mult_in1 = 32'hxxxxxxxx;
                mult_start = 0;
                mult_acc0 = 32'hxxxxxxxx;
                mult_in0 = 32'hxxxxxxxx;
                mult_in1 = 32'hxxxxxxxx;

-       
+

                alu_in0 = 32'hxxxxxxxx;
                alu_in1 = 32'hxxxxxxxx;
                alu_op = 4'hx;  /* hax! */
                alu_setflags = 1'bx;
                alu_in0 = 32'hxxxxxxxx;
                alu_in1 = 32'hxxxxxxxx;
                alu_op = 4'hx;  /* hax! */
                alu_setflags = 1'bx;

-               
+
+               jmp = 1'b0;
+               jmppc = 32'h00000000;
+

                casez (insn)
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin
                casez (insn)
                `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
                begin


@@ -159,11 +171,14 @@ module Execute(
                begin end
                `DECODE_BRANCH:
                begin
                begin end
                `DECODE_BRANCH:
                begin

-                       outpc = pc + op0;
-                       if(insn[24]) begin
-                               next_write_reg = 1;
-                               next_write_num = 4'hE; /* link register */
-                               next_write_data = pc + 32'h4;
+                       if(!inbubble) begin
+                               jmppc = pc + op0 + 32'h8;
+                               if(insn[24]) begin
+                                       next_write_reg = 1;
+                                       next_write_num = 4'hE; /* link register */
+                                       next_write_data = pc - 32'h4;
+                               end
+                               jmp = 1'b1;

                        end
                end                     /* Branch */
                `DECODE_LDCSTC,         /* Coprocessor data transfer */
                        end
                end                     /* Branch */
                `DECODE_LDCSTC,         /* Coprocessor data transfer */


@@ -229,8 +244,8 @@ module ALU(
        output reg [31:0] cpsr_out,
        output reg setres
 );
        output reg [31:0] cpsr_out,
        output reg setres
 );

-       wire [31:0] res;
-       wire flag_n, flag_z, flag_c, flag_v, setres;
+       reg [31:0] res;
+       reg flag_n, flag_z, flag_c, flag_v;

        wire [32:0] sum, diff, rdiff;
        wire sum_v, diff_v, rdiff_v;
 
        wire [32:0] sum, diff, rdiff;
        wire sum_v, diff_v, rdiff_v;