Makefile: Add 'auto' target to verilog-modeify.

[firearm.git] / BlockRAM.v

diff --git a/BlockRAM.v b/BlockRAM.v
index e0eceeb8009caa4c458c95301ca5666d6fb8e09a..091c749aef6f8f482bfbfe3025c881608d1696ff 100644 (file)
--- a/BlockRAM.v
+++ b/BlockRAM.v
@@ -31,11 +31,11 @@ module BlockRAM(
        always @(posedge clk)
        begin
                if (bus_wr && decode)
-                       data[ramaddr[13:2]] = bus_wdata;
+                       data[ramaddr[13:2]] <= bus_wdata;
                
                /* This is not allowed to be conditional -- stupid Xilinx
                 * blockram. */
-               temprdata <= data[ramaddr[13:2]];
+               temprdata <= (bus_wr && decode) ? bus_wdata : data[ramaddr[13:2]];
                lastread <= ramaddr;
        end
 endmodule